Ultra-efficient fundamental fuzzy Min and Max circuits are proposed in this paper using 3 CNTFETs. These are much energy-efficient compared to the state-of-the-art previous designs of Min and Max circuits, which are vastly superior to other models. This is due to the lack of a direct current path (between the inputs and GND /V_DD) and the low output resistance. The superiority of the proposed Min and Max Circuits are technically described and proved. At the next step, an applied circuit, the ternary half-adder is developed based on the proposed Min and Max circuits. In these suggestions, all parts of half-adder, successor, and predecessor circuits are introduced based on ternary gates. The simulation results, as obtained through extensive simulations using Synopsys HSPICE and the 32 nm Stanford comprehensive CNTFET model, demonstrate that proposed Min and Max circuits are 22 times (%95.5) and 38 times (%97.39) more energy-efficient with a 0.5fF load compared to the best previous work, respectively. Furthermore, the proposed half-adder is %39 more energy-efficient with a 0.5fF load, compared to the previous work.

本文提出了使用 3 个 CNTFET 的超高效基本模糊最小和最大电路。与先前最先进的 Min 和 Max 电路设计相比，它们的能效更高，后者远远优于其他模型。这是由于缺乏直流路径（在输入和 GND /V _{DD 之间}) 和低输出电阻。从技术上描述和证明了所提议的最小和最大电路的优越性。在下一步，一个应用电路，三元半加器是基于建议的最小和最大电路开发的。在这些建议中，半加器、后继电路和前驱电路的所有部分都是基于三元门引入的。仿真结果是通过使用 Synopsys HSPICE 和 32 nm 斯坦福综合 CNTFET 模型的广泛仿真获得的，表明所提出的 Min 和 Max 电路的能效提高了 22 倍 (%95.5) 和 38 倍 (%97.39)，具有 0.5fF负载分别与以前的最佳工作相比。此外，与之前的工作相比，所提出的半加器在 0.5fF 负载下的能效提高了 39%。