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Comparative Analysis of the Design Techniques for Low Leakage SRAMs at 32nm
Microprocessors and Microsystems ( IF 1.9 ) Pub Date : 2021-06-10 , DOI: 10.1016/j.micpro.2021.104281
Monica Gupta , Kirti Gupta , Neeta Pandey

This paper presents a comprehensive overview of leakage reduction techniques prevailing in Static Random Access Memories (SRAMs) by classifying them in three categories namely latch, bitline and read port. The performance of the techniques are evaluated in terms of leakage reduction capability along with the impact on read performance and hold stability through extensive simulative investigations at 32 nm technology node by taking conventional SRAM cell as reference. Further, as SRAMs are susceptible to inter-die as well as intra-die process variations, the performance at different PVT corners is also captured to demonstrate the efficacy of each technique under PVT variations. It is found that among the techniques used for reducing latch leakages, Multi-threshold CMOS technique possess the highest leakage reduction capabilities followed by Drowsy mode and Substrate-bias techniques. The results also indicate that Negative word line technique is more effective at low supply voltages whereas the Leakage biased bitline technique is more effective at high supply voltages for reducing bitline leakages. Amongst the read port leakage reduction techniques, Stack-effect and Dynamic control of power supply rail techniques are capable of suppressing the leakages at high voltages whereas Virtual cell ground technique is more efficacious at low voltages. The impact of technology scaling on SRAM cell performance with leakage reduction techniques is also studied. For the sake of completeness, suggestions are put forward for adopting a particular technique to address leakages at latch, bitline and read port levels.



中文翻译:

32nm低泄漏SRAM设计技术对比分析

本文通过将静态随机存取存储器 (SRAM) 中的泄漏减少技术分为三类,即锁存器、位线和读取端口,全面概述了在静态随机存取存储器 (SRAM) 中流行的泄漏减少技术。通过以传统 SRAM 单元为参考,在 32 nm 技术节点上进行广泛的模拟研究,在减少泄漏能力以及对读取性能和保持稳定性的影响方面评估了这些技术的性能。此外,由于 SRAM 容易受到芯片间和芯片内工艺变化的影响,因此还捕获了不同 PVT 角落的性能,以证明每种技术在 PVT 变化下的功效。发现在用于减少闩锁泄漏的技术中,多阈值 CMOS 技术拥有最高的泄漏减少能力,其次是昏昏欲睡模式和衬底偏置技术。结果还表明负字线技术在低电源电压下更有效,而泄漏偏置位线技术在高电源电压下更有效,以减少位线泄漏。在读取端口泄漏减少技术中,电源轨技术的堆栈效应和动态控制能够抑制高电压下的泄漏,而虚拟单元接地技术在低电压下更有效。还研究了技术缩放对采用泄漏减少技术的 SRAM 单元性能的影响。为了完整起见,提出了采用特定技术解决闩锁泄漏问题的建议,

更新日期:2021-06-10
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