Demand for high-speed wireless broadband internet service is ever increasing. Multiple-input-multiple-output (MIMO) Wireless LAN (WLAN) is becoming a promising solution for such high-speed internet service requirements. This paper proposes a novel algorithm to efficiently model the address generation circuitry of the MIMO WLAN interleaver. The interleaver used in the MIMO WLAN transceiver has three permutation steps involving floor function whose hardware implementation is the most challenging task due to the absence of corresponding digital hardware. In this work, we propose an algorithm with a mathematical background for the address generator, eliminating the need for floor function. The algorithm is converted into digital hardware for implementation on the reconfigurable FPGA platform. Hardware structure for the complete interleaver, including the read address generator and memory module, is designed and modeled in VHDL using Xilinx Integrated Software Environment (ISE) utilizing embedded memory and DSP blocks of Spartan 6 FPGA. The functionality of the proposed algorithm is verified through exhaustive software simulation using ModelSim software. Hardware testing is carried out on Zynq 7000 FPGA using Virtual Input Output (VIO) and Integrated Logic Analyzer (ILA) core. Comparisons with few recent similar works, including the conventional Look-Up Table (LUT) based technique, show the superiority of our proposed design in terms of maximum improvement in operating frequency by 196.83%, maximum reduction in power consumption by 74.27%, and reduction of memory occupancy by 88.9%. In the case of throughput, our design can deliver 8.35 times higher compared to IEEE 802.11n requirement.

中文翻译：

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用于 MIMO WLAN 应用的高吞吐量资源高效可重构交织器

对高速无线宽带互联网服务的需求不断增加。多输入多输出 (MIMO) 无线局域网 (WLAN) 正在成为满足此类高速互联网服务需求的有前途的解决方案。本文提出了一种新颖的算法来有效地模拟 MIMO WLAN 交织器的地址生成电路。MIMO WLAN 收发器中使用的交织器具有三个涉及楼层函数的置换步骤，由于缺少相应的数字硬件，其硬件实现是最具挑战性的任务。在这项工作中，我们为地址生成器提出了一种具有数学背景的算法，消除了对楼层函数的需要。该算法被转换为数字硬件以在可重构FPGA平台上实现。完整交织器的硬件结构，包括读取地址生成器和存储器模块，是使用 Xilinx 集成软件环境 (ISE) 在 VHDL 中设计和建模的，利用嵌入式存储器和 Spartan 6 FPGA 的 DSP 块。所提出算法的功能通过使用 ModelSim 软件的详尽软件仿真得到验证。使用虚拟输入输出 (VIO) 和集成逻辑分析器 (ILA) 内核在 Zynq 7000 FPGA 上执行硬件测试。与最近几项类似工作的比较，包括传统的基于查找表 (LUT) 的技术，表明我们提出的设计在工作频率最大提高 196.83%、功耗最大降低 74.27% 和减少方面的优越性。内存占用率为 88.9%。在吞吐量方面，我们的设计可以提供比 IEEE 802 高 8.35 倍的数据。