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Understanding Cache Compression
ACM Transactions on Architecture and Code Optimization ( IF 1.5 ) Pub Date : 2021-06-08 , DOI: 10.1145/3457207
Daniel Rodrigues Carvalho 1 , André Seznec 1
Affiliation  

Hardware cache compression derives from software-compression research; yet, its implementation is not a straightforward translation, since it must abide by multiple restrictions to comply with area, power, and latency constraints. This study sheds light on the challenges of adopting compression in cache design—from the shrinking of the data until its physical placement. The goal of this article is not to summarize proposals but to put in evidence the solutions they employ to handle those challenges. An in-depth description of the main characteristics of multiple methods is provided, as well as criteria that can be used as a basis for the assessment of such schemes. It is expected that this article will ease the understanding of decisions to be taken for the design of compressed systems and provide directions for future work.

中文翻译:

了解缓存压缩

硬件缓存压缩源于软件压缩研究;然而,它的实现并不是一个简单的翻译,因为它必须遵守多种限制以符合面积、功率和延迟限制。这项研究揭示了在缓存设计中采用压缩技术所面临的挑战——从数据的缩减到其物理放置。本文的目的不是总结提案,而是证明他们用来应对这些挑战的解决方案。提供了对多种方法的主要特征的深入描述,以及可用作评估此类方案的基础的标准。预计本文将有助于理解为设计压缩系统而需要做出的决策,并为未来的工作提供方向。
更新日期:2021-06-08
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