As technology scales, radiation induced soft errors create more complex error patterns in memories with a single particle corrupting several bits. This poses a challenge to the Error Correction Codes (ECCs) traditionally used to protect memories that can correct only single bit errors. During the last decade, a number of codes have been developed to correct the emerging error patterns, focusing initially on double adjacent errors and later on three bit burst errors. However, as the memory cells get smaller and smaller, the error patterns created by radiation will continue to change and thus new codes will be needed. In addition, the memory layout and the technology used may also make some patterns more likely than others. For example, in some memories, there maybe elements that separate blocks of bits in a word, making errors that affect two blocks less likely. Finally, for a given memory, depending on the data stored, some error patterns may be more critical than others. For example, if numbers are stored in the memory, in most cases, errors on the more significant bits have a larger impact. Therefore, for a given memory and application, to achieve optimal protection, we would like to have a code that corrects a given set of patterns. This is not possible today as there is a limited number of code choices available in terms of correctable error patterns and word lengths. However, most of the codes used to protect memories are linear block codes that have a regular structure and which design can be automated. In this paper, we propose the automation of error correction code design for memory protection. To that end, we introduce a software tool that given a word length and the error patterns that need to be corrected, produces a linear block code described by its parity check matrix and also the bit placement. The benefits of this automated design approach are illustrated with several case studies. Finally, the tool is made available so that designers can easily produce custom error correction codes for their specific needs.

中文翻译：

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保护内存免受软错误的影响：可定制的纠错码案例

随着技术规模的扩大，辐射引起的软错误会在存储器中产生更复杂的错误模式，单个粒子会破坏多个位。这对传统上用于保护只​​能纠正单个位错误的存储器的纠错码 (ECC) 提出了挑战。在过去的十年中，已经开发了许多代码来纠正新出现的错误模式，最初关注双相邻错误，后来关注三位突发错误。然而，随着存储单元变得越来越小，由辐射产生的错误模式将继续改变，因此将需要新的代码。此外，内存布局和使用的技术也可能使某些模式比其他模式更有可能。例如，在某些存储器中，可能存在将字中的位块分开的元素，使影响两个块的错误的可能性降低。最后，对于给定的内存，根据存储的数据，某些错误模式可能比其他错误模式更严重。例如，如果数字存储在内存中，在大多数情况下，较高位的错误会产生更大的影响。因此，对于给定的内存和应用程序，为了实现最佳保护，我们希望有一个代码来纠正给定的一组模式。这在今天是不可能的，因为在可纠正的错误模式和字长方面可用的代码选择数量有限。然而，用于保护存储器的大多数代码是具有规则结构并且可以自动设计的线性分组代码。在本文中，我们提出了用于内存保护的纠错码设计的自动化。为此，我们引入了一个软件工具，它给出了一个字长和需要纠正的错误模式，产生一个由奇偶校验矩阵和位放置描述的线性块码。几个案例研究说明了这种自动化设计方法的好处。最后，该工具可用，以便设计人员可以轻松生成满足其特定需求的自定义纠错代码。