This paper presents a low-power single-channel 8-bit loop-unrolled (LU) successive approximation register (SAR) analog-to-digital-converter (ADC) with a novel common-mode adaptive background comparator offset calibration scheme. LU-SAR ADCs use multiple comparators to reduce the SAR loop delay. Offset mismatch between the comparators severely degrades the effective resolution. This paper addresses the common-mode voltage variation in the LU-SAR architecture due to comparator kickback and the problems related to the common-mode dependency of the comparator offset. The proposed offset calibration scheme ensures that the comparators are calibrated at the same input common-mode voltage at which they each operate during the SAR conversion to prevent the common-mode dependent offset mismatch between them. Moreover, the proposed ADC design exploits the common-mode variation immunity of the proposed calibration scheme to optimize the figure-of-merit (FoM). The prototype ADC manufactured in 28nm FDSOI CMOS achieves 42.57dB signal-to-noise-and-distortion ratio and 22.8fJ/conv.-step FoM at 800MS/s with near Nyquist frequency input, and occupies an area of 0.0037mm 2 .

中文翻译：

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具有 28 nm FDSOI 共模自适应背景偏移校准功能的 8 位 800 MS/s 环路展开 SAR ADC


本文提出了一种低功耗单通道 8 位循环展开 (LU) 逐次逼近寄存器 (SAR) 模数转换器 (ADC)，具有新颖的共模自适应背景比较器偏移校准方案。 LU-SAR ADC 使用多个比较器来减少 SAR 环路延迟。比较器之间的偏移不匹配严重降低了有效分辨率。本文解决了 LU-SAR 架构中由于比较器反冲引起的共模电压变化以及与比较器偏移的共模依赖性相关的问题。所提出的失调校准方案确保比较器在 SAR 转换期间各自工作的相同输入共模电压下进行校准，以防止它们之间的共模相关失调失配。此外，所提出的 ADC 设计利用所提出的校准方案的共模变化抗扰度来优化品质因数 (FoM)。采用28nm FDSOI CMOS制造的原型ADC在接近奈奎斯特频率输入的800MS/s下实现了42.57dB信噪比和22.8fJ/转换步FoM，并且占据了0.0037mm 2 的面积。