An asynchronous event-driven approach to clocking and timing control is explored in the context of pipelined ADCs. It is shown how a conventional global clock tree can be replaced by localized control units coordinated through inter-stage communication protocols. The approach is found to yield many compelling advantages in terms of power efficiency, speed, robustness, and reconfigurability. It is shown how these benefits are particularly well leveraged when used in combination with dynamic-power residue amplifiers such as ring amplifiers. Several challenges also arise: re-synchronization of the digital outputs, mitigation of possible deadlock scenarios, and robust timing control configuration. Solutions to these problems are presented. Two single-channel 11-bit 1.5-bit/stage pipelined ADC designs are fabricated in a 16nm CMOS technology, each with a different implementation approach to the asynchronous control units. The trade-offs of both approaches are considered. At 1 GS/s the fastest prototype achieves 59.5 dB SNDR and 75.9 dB SFDR at Nyquist, consuming 10.9 mW including reference regulator. Due to fully-dynamic operation, it maintains a near-constant Walden Figure of Merit (FoM) of 14 fJ/conversion-step from 1 MS/s to 1 GS/s.

中文翻译：

---

流水线 ADC 中的异步事件驱动时钟和控制


在流水线 ADC 的背景下探索了一种异步事件驱动的时钟和时序控制方法。展示了如何用通过级间通信协议协调的本地控制单元来取代传统的全局时钟树。人们发现该方法在功效、速度、稳健性和可重构性方面具有许多引人注目的优势。它展示了当与动态功率剩余放大器（例如环形放大器）结合使用时，如何特别充分地利用这些优势。还出现了一些挑战：数字输出的重新同步、缓解可能的死锁情况以及强大的时序控制配置。提出了这些问题的解决方案。两个单通道 11 位 1.5 位/级流水线 ADC 设计采用 16nm CMOS 技术制造，每个设计都采用不同的异步控制单元实现方法。考虑了两种方法的权衡。在 1 GS/s 速度下，最快的原型在奈奎斯特条件下可实现 59.5 dB SNDR 和 75.9 dB SFDR，消耗 10.9 mW（包括参考稳压器）。由于全动态操作，它在从 1 MS/s 到 1 GS/s 的过程中保持了近乎恒定的 Walden 品质因数 (FoM)，即 14 fJ/转换步长。