Pairs trading is a solidly profitable strategy in the algorithmic trading area, and an important step of this strategy is selecting pairs of stocks. Compared with other existing pairs selection approaches, the Engle-Granger cointegration is more stable and reliable. Nowadays, as trading is becoming faster and faster in stock markets all over the world, it is necessary to accelerate the pairs selection process to increase potential profits. However, intensive computations and complicated data flow in the cointegration approach bring challenges to hardware acceleration. In this paper, for the first time, we propose an efficient and hardware-friendly computing scheme to accelerate the Engle-Granger cointegration. Besides, a novel algorithmic strength reduction strategy and approximation methods are used to significantly reduce the complexity of the proposed scheme. Based on the improved algorithm, both FPGA and ASIC accelerators are developed. The implementation results show that our FPGA and ASIC accelerators perform $36\times $ and $207\times $ faster than GPU, respectively. Thus, our design can significantly reduce the latency of the pairs selection process, and make more profit for investors and traders.

中文翻译：

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用于改进配对交易中 Engle-Granger 协整的低延迟硬件加速器


配对交易是算法交易领域中一种稳定盈利的策略，该策略的一个重要步骤是选择股票配对。与其他现有的配对选择方法相比，Engle-Granger 协整更加稳定可靠。如今，随着世界各地股票市场的交易变得越来越快，有必要加快配对选择过程以增加潜在利润。然而，协整方法中的密集计算和复杂数据流给硬件加速带来了挑战。在本文中，我们首次提出了一种高效且硬件友好的计算方案来加速 Engle-Granger 协整。此外，采用新颖的算法强度降低策略和近似方法来显着降低所提出方案的复杂性。基于改进算法，开发了FPGA和ASIC加速器。实施结果表明，我们的 FPGA 和 ASIC 加速器的执行速度分别比 GPU 快 36 倍和 207 倍。因此，我们的设计可以显着减少配对选择过程的延迟，并为投资者和交易者带来更多利润。