Conventional hardened cells are not robust enough to single event upset (SEU) in 28nm technology due to the scaling of the transistors. High soft error rate is caused by particle striking at cells and logic circuit in SRAM. This work proposes an SEU robust dual access 12T (DA-12T) SRAM with a radiation hardened crossbar-based peripheral circuit (CBPC). The proposed cell with 209% area penalty is more SEU robust than most cells. The CBPC can reduce the read failure rate of SRAMs. The new sense amplifier ensures the correct and rapid reading operation speed when suffering read disturbance. The experiment results show that the SEU cross-section of proposed cell is 60% of standard cell with dummy. Almost no read failure is observed in SRAM with CPBC when operational frequency exceeds 40MHz. Further investigation indicated that DA-12T cell and well isolation technique can reduce the read failure rate.

中文翻译：

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采用 28nm CMOS 技术、具有基于 Crossbar 的外围电路的抗辐射 12T SRAM


由于晶体管的尺寸缩小，传统的硬化单元在 28 纳米技术中不足以抵抗单粒子翻转 (SEU)。高软错误率是由粒子撞击SRAM中的单元和逻辑电路造成的。这项工作提出了一种具有抗辐射基于交叉开关的外围电路 (CBPC) 的 SEU 鲁棒双存取 12T (DA-12T) SRAM。所提出的具有 209% 面积损失的单元比大多数单元更具有 SEU 鲁棒性。 CBPC可以降低SRAM的读取失败率。新型读出放大器确保在遭受读取干扰时正确且快速的读取操作速度。实验结果表明，所提出的电池的SEU横截面是带有假体的标准电池的60%。当工作频率超过 40MHz 时，带有 CPBC 的 SRAM 几乎没有观察到读取失败的情况。进一步研究表明DA-12T细胞和孔隔离技术可以降低读取失败率。