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Efficient Hardware Architecture of Convolutional Neural Network for ECG Classification in Wearable Healthcare Device
IEEE Transactions on Circuits and Systems I: Regular Papers ( IF 5.2 ) Pub Date : 2021-04-23 , DOI: 10.1109/tcsi.2021.3072622
Jiahao Lu , Dongsheng Liu , Zilong Liu , Xuan Cheng , Lai Wei , Cong Zhang , Xuecheng Zou , Bo Liu

Nowadays, with the increasing shortage of traditional medical resources, the existing portable monitoring healthcare device is no longer satisfactory. Thus, wearable healthcare device with diagnostic capability is becoming much more desirable. However, the design of wearable healthcare device faces the challenge of limited hardware resource and high diagnostic accuracy. In this paper, an efficient hardware architecture is proposed to implement a 1-D CNN with global average pooling (GAP) specially for embedded electrocardiogram (ECG) classification. The GAP is implemented by substituting division into shifting operation without extra computing resource consumption and it can largely reduce the parameters of the network. The fully pipelined processing unit (PU) array is designed to increase computing efficiency. A sign bit based dynamic activation strategy is developed for removing redundant multiplications and resource consumption of ReLU. The proposed efficient hardware architecture is implemented on Xilinx Zynq ZC706 board and achieves an average performance of 25.7 GOP/s under 200-MHz with resource consumption of 1538 LUT, which makes resource efficiency improved by more than $3\times $ compared with non-optimized case. The averaged classification accuracy of five ECG beats classes is 99.10%. In brief, the proposed efficient hardware design is prospective for wearable healthcare device especially in ECG classification area.

中文翻译:


用于可穿戴医疗设备中心电图分类的卷积神经网络的高效硬件架构



如今,随着传统医疗资源的日益短缺,现有的便携式监护医疗设备已不能令人满意。因此,具有诊断功能的可穿戴医疗设备变得更加令人向往。然而,可穿戴医疗设备的设计面临着硬件资源有限和诊断准确性高的挑战。本文提出了一种高效的硬件架构来实现具有全局平均池化(GAP)的一维 CNN,专门用于嵌入式心电图(ECG)分类。 GAP通过将除法替换为移位操作来实现,不需要额外的计算资源消耗,可以大大减少网络的参数。全流水线处理单元(PU)阵列旨在提高计算效率。开发了一种基于符号位的动态激活策略,用于消除 ReLU 的冗余乘法和资源消耗。所提出的高效硬件架构在 Xilinx Zynq ZC706 板上实现,在 200 MHz 下实现了 25.7 GOP/s 的平均性能,资源消耗为 1538 个 LUT,与非优化相比,资源效率提高了 3 倍以上案件。五个心电心跳类别的平均分类准确率为 99.10%。简而言之,所提出的高效硬件设计对于可穿戴医疗设备尤其是心电图分类领域具有前景。
更新日期:2021-04-23
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