Spread spectrum clocking (SSC) conventionally uses frequency modulation (FM) to suppress digital switching noise in the frequency domain. While clock-FM effectively reduces spectral noise peaks, it maintains the synchronous operation per cycle with total noise unchanged. In this paper, we introduce plesiochronous design as a general applicable de-synchronization solution for the spectral switching noise optimization with guaranteed quality-of-service. By modeling on-chip aperiodic supply current as a poly-cyclostationary random process, we theoretically prove that digital plesiochronous design contributes to reducing both, total and peak switching noise, in a harmonic frequency band of interest logarithmically proportional to the number of adopted clock domains over the synchronous baseline. A complete framework is also developed to implement plesiochronous design with the optimal clock domain partitioning and FIFO-based synchronization that features a minimum depth of six by employing Johnson encoding fully compatible with mainstream design flow. Validated on a 130nm pipelined FFT test chip across 25 dies thus taking process variations into account, our plesiochronous SSC achieves on average 5.1dB total power reductions in addition to 12.8dB peak power reductions of substrate noise at the clock fundamental frequency, which match our predictions, with only marginal hardware overhead in terms of cell area and power consumption.

中文翻译：

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具有保证 QoS 的准同步扩频时钟，可降低带内切换噪声


扩频时钟 (SSC) 通常使用频率调制 (FM) 来抑制频域中的数字开关噪声。虽然时钟调频有效降低频谱噪声峰值，但它保持每个周期的同步操作，总噪声不变。在本文中，我们引入准同步设计作为一种通用的去同步解决方案，用于保证服务质量的频谱切换噪声优化。通过将片上非周期电源电流建模为多周期平稳随机过程，我们从理论上证明，数字准同步设计有助于在与所采用的时钟域数量成对数比例的感兴趣的谐波频带中降低总开关噪声和峰值开关噪声超过同步基线。还开发了一个完整的框架，通过采用与主流设计流程完全兼容的约翰逊编码，实现具有最佳时钟域分区和基于 FIFO 的同步的准同步设计，其最小深度为 6。在跨 25 个芯片的 130nm 流水线 FFT 测试芯片上进行验证，考虑到工艺变化，我们的准同步 SSC 平均总功率降低了 5.1dB，时钟基频下的衬底噪声峰值功率降低了 12.8dB，这与我们的预测相符，在单元面积和功耗方面只有边际硬件开销。