With the continuous scaling-down of transistors, the soft error issue of the combinational circuit becomes more serious. Triple Modular Redundancy (TMR) and Gate-Sizing (GS) are commonly used hardening methods for combinational circuits. However, the traditional TMR method is often applied at the module level, causing a large area overhead. Therefore, to explore the feasibility of refined and more general TMR, a General Efficient TMR (GE-TMR) method is proposed in this paper. Furthermore, since the hardening process is a multi-objective optimization problem, a Solution Distribution Optimized NSGA-II (SDON) algorithm is proposed. It features a trade-off between Soft Error Rate (SER), delay, and area. Based on the SDON, we systematically characterized and compared the three hardening methods, which are GE-TMR, GS, and MIX (a hybrid application of GE-TMR and GS). The experimental results show that GE-TMR can provide lower SER solutions (SER reduction >88%) than GS (SER reduction >85%) when the area overhead >200%. By combining GE-TMR and GS, in the interval of 100%<; area overhead <; 200%, the solutions of MIX have lower SER (SER reduction >81%) than the two hardening methods optimized separately (SER reduction of 64% and 80% for GE-TMR and GS, respectively).

中文翻译：

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用于针对软错误的组合电路强化的通用高效 TMR 和改进的多目标优化框架


随着晶体管尺寸的不断缩小，组合电路的软错误问题变得更加严重。三重模块冗余（TMR）和栅极尺寸（GS）是组合电路常用的强化方法。然而，传统的TMR方法往往应用于模块级，造成较大的面积开销。因此，为了探索精细化和更通用的TMR的可行性，本文提出了一种通用高效TMR（GE-TMR）方法。此外，由于强化过程是一个多目标优化问题，因此提出了解决方案分布优化NSGA-II（SDON）算法。它具有软错误率 (SER)、延迟和面积之间的权衡。基于SDON，我们系统地表征和比较了三种硬化方法，即GE-TMR、GS和MIX（GE-TMR和GS的混合应用）。实验结果表明，当面积开销>200%时，GE-TMR可以提供比GS（SER降低>85%）更低的SER解决方案（SER降低>88%）。通过GE-TMR和GS的结合，在100%<的区间内；面积开销<； 200%，MIX 的解决方案比单独优化的两种硬化方法（GE-TMR 和 GS 的 SER 分别降低 64% 和 80%）具有更低的 SER（SER 降低 >81%）。