As quantum computers become more affordable and commonplace, existing security systems that are based on classical cryptographic primitives, such as RSA and Elliptic Curve Cryptography ( ECC ), will no longer be secure. Hence, there has been interest in designing post-quantum cryptographic ( PQC ) schemes, such as those based on lattice-based cryptography ( LBC ). The potential of LBC schemes is evidenced by the number of such schemes passing the selection of NIST PQC Standardization Process Round-3. One such scheme is the Crystals-Dilithium signature scheme, which is based on the hard module-lattice problem. However, there is no efficient implementation of the Crystals-Dilithium signature scheme. Hence, in this article, we present a compact hardware architecture containing elaborate modular multiplication units using the Karatsuba algorithm along with smart generators of address sequence and twiddle factors for NTT, which can complete polynomial addition/multiplication with the parameter setting of Dilithium in a short clock period. Also, we propose a fast software/hardware co-design implementation on Field Programmable Gate Array ( FPGA ) for the Dilithium scheme with a tradeoff between speed and resource utilization. Our co-design implementation outperforms a pure C implementation on a Nios-II processor of the platform Altera DE2-115, in the sense that our implementation is 11.2 and 7.4 times faster for signature and verification, respectively. In addition, we also achieve approximately 51% and 31% speed improvement for signature and verification, in comparison to the pure C implementation on processor ARM Cortex-A9 of ZYNQ-7020 platform.

中文翻译：

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Crystals-Dilithium签名方案的软硬件协同设计

随着量子计算机变得越来越便宜和普遍，现有的基于经典密码原语的安全系统，如 RSA 和椭圆曲线密码学(ECC)，将不再安全。因此，人们对设计产生了兴趣后量子密码学(质量控制) 方案，例如那些基于基于格的密码学(LBC）。通过 NIST PQC 标准化流程第三轮选择的此类方案的数量证明了 LBC 方案的潜力。一种这样的方案是 Crystals-Dilithium 签名方案，它基于硬模块 - 晶格问题。然而，Crystals-Dilithium 签名方案没有有效的实现。因此，在本文中，我们提出了一个紧凑的硬件架构，其中包含使用 Karatsuba 算法的精细模乘单元以及 NTT 的地址序列和旋转因子的智能生成器，它可以在很短的时间内完成多项式加法/乘法与 Dilithium 的参数设置时钟周期。此外，我们提出了一种快速的软件/硬件协同设计实施方案现场可编程门阵列(FPGA) 用于在速度和资源利用率之间进行权衡的 Dilithium 方案。我们的协同设计实现优于平台 Altera DE2-115 的 Nios-II 处理器上的纯 C 实现，因为我们的实现在签名和验证方面分别快了 11.2 倍和 7.4 倍。此外，与 ZYNQ-7020 平台的处理器 ARM Cortex-A9 上的纯 C 实现相比，我们还实现了约 51% 和 31% 的签名和验证速度提升。