Recycling of used ICs as new replacement parts in maintaining older electronic systems is a serious reliability concern. This paper presents a novel approach to estimate the operational age of CMOS chips by measuring I_DDQ, the quiescent current from power supply or the total leakage current in steady state. This current decreases as the circuit ages, largely due to the increase in the magnitude of the PMOS transistor threshold voltage caused by negative bias temperature instability (NBTI). We exploit the fact that the impact of NBTI on an individual transistor depends upon the operational stress based upon the duration of its ON state. Novelty of our technique is a normalized difference, ΔI, computed from current measurements at two input test patterns and is proposed as a self referencing circuit age indicator. The first pattern is chosen such that its I_DDQ is controlled by a large number of minimally stressed PMOS transistors; for the other the I_DDQ is controlled by approximately equal number of highly stressed PMOS transistors. The difference between these two I_DDQ values increases with the circuit age. This approach requires no hardware modification in the circuit and, hence, can be applied to legacy ICs. Simulation results show that we can reliably identify recycled ICs that have been used for as little as six months.

回收使用过的 IC 作为新的更换部件来维护旧电子系统是一个严重的可靠性问题。本文提出了一种通过测量I _{D D Q}、电源静态电流或稳态总泄漏电流来估计 CMOS 芯片工作寿命的新方法。该电流随着电路老化而降低，主要是由于负偏置温度不稳定性 (NBTI) 导致 PMOS 晶体管阈值电压的幅度增加。我们利用这样一个事实，即 NBTI 对单个晶体管的影响取决于基于其导通状态持续时间的操作应力。我们的技术的新颖性，是一个归一化，Δ我，根据两个输入测试模式的电流测量值计算得出，建议作为自参考电路老化指标。选择第一种模式，使其I _{D D Q}由大量最小应力 PMOS 晶体管控制；对于另一个I _{D D Q}由大约相等数量的高应力 PMOS 晶体管控制。这两个I _{D D Q}值之间的差异随着电路年龄的增加而增加。这种方法不需要对电路进行硬件修改，因此可以应用于传统 IC。仿真结果表明，我们可以可靠地识别使用时间短至六个月的回收 IC。