We present a novel framework for designing multiplierless kernel machines that can be used on resource-constrained platforms like intelligent edge devices. The framework uses a piecewise linear (PWL) approximation based on a margin propagation (MP) technique and uses only addition/subtraction, shift, comparison, and register underflow/overflow operations. We propose a hardware-friendly MP-based inference and online training algorithm that has been optimized for a Field Programmable Gate Array (FPGA) platform. Our FPGA implementation eliminates the need for DSP units and reduces the number of LUTs. By reusing the same hardware for inference and training, we show that the platform can overcome classification errors and local minima artifacts that result from the MP approximation. Using the FPGA platform, we also show that the proposed multiplierless MP-kernel machine demonstrates superior performance in terms of power, performance, and area compared to other comparable implementations.

中文翻译：

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用于节能边缘设备的无乘法器 MP-Kernel 机器

我们提出了一种新颖的框架，用于设计可在资源受限平台（如智能边缘设备）上使用的无乘数内核机器。该框架使用基于边际传播 (MP) 技术的分段线性 (PWL) 近似，并且仅使用加法/减法、移位、比较和寄存器下溢/上溢操作。我们提出了一种硬件友好的基于 MP 的推理和在线训练算法，该算法已针对现场可编程门阵列 (FPGA) 平台进行了优化。我们的 FPGA 实现消除了对 DSP 单元的需求并减少了 LUT 的数量。通过重用相同的硬件进行推理和训练，我们表明该平台可以克服 MP 近似导致的分类错误和局部最小值伪影。使用FPGA平台，