Integrated circuits operating in the near/subthreshold region offer low energy consumption. However, due to the constrained voltage scalability of SRAMs, efficient power delivery is difficult to achieve. A traditional implementation would require at least two distinct voltage supplies generated by possibly two power converters. In this article, a new implementation for near/subthreshold operation is presented. The proposed implementation consists of a new “converter-free” design based on a three-level voltage stack operating at 1.8 V ± 5%. Here, the leakage current from the SRAMs in the top stack is recycled to sustain the near/subthreshold operation of the logic circuits in the two lower stacks. A test chip with the proposed voltage-stacking technique was implemented in a 28-nm low- Vth (LVT) fully depleted silicon on insulator (FDSOI) technology. The test chip is an ultralow-power advanced system-on-chip (SoC) consisting of an RISC-V core, a coarse-grained reconfigurable accelerator, and peripherals. The SoC uses a current sink and an adaptive body-bias controller for voltage regulation of the intermediate voltage rails between the stacks. The proposed system achieves up to 95% power delivery efficiency with negligible area overhead (~ 1%). The silicon measurement shows that the system energy efficiency is improved by 1.6× on average, and the energy consumption is reduced by 37% on average compared to the flat implementation.

中文翻译：

---

使用电压叠加进行近/亚阈值操作的无转换器供电


在近阈值/亚阈值区域运行的集成电路能耗较低。然而，由于 SRAM 的电压可扩展性有限，因此很难实现高效的电力传输。传统的实现将需要至少两个不同的电压源，这两个电压源可能由两个电源转换器产生。在本文中，提出了近/亚阈值操作的新实现。所提出的实施方案包括一种新的“无转换器”设计，该设计基于工作电压为 1.8 V ± 5% 的三电平电压堆栈。这里，来自顶部堆栈中的 SRAM 的漏电流被回收以维持两个较低堆栈中的逻辑电路的接近/亚阈值操作。采用所提出的电压堆叠技术的测试芯片是在 28 nm 低 Vth (LVT) 全耗尽绝缘体上硅 (FDSOI) 技术中实现的。该测试芯片是一款超低功耗先进片上系统（SoC），由RISC-V内核、粗粒度可重构加速器和外设组成。 SoC 使用电流吸收器和自适应体偏置控制器来调节堆栈之间的中间电压轨的电压。所提出的系统可实现高达 95% 的电力传输效率，而面积开销可以忽略不计 (~ 1%)。硅测结果表明，与扁平化实现相比，系统能效平均提升1.6倍，能耗平均降低37%。