Aerospace applications are attractive candidates to embed artificial neural networks despite their excellent parallel processing capability and reduced energy consumption. Nonetheless, the long-term exposure to incidence levels of ionizing radiation may degrade their physical components reducing, therefore, their reliability and expected lifetime. Thus, it is mandatory to face the challenge of enhancing the radiation hardening characteristics of a neural circuit before operating in harsh environments. A possible solution to substantially reduce long-term spurious effects caused by ionizing radiation [referred to as total ionizing dose (TID)] is to change the conventional rectangular MOS gate geometry to a nonstandard topology referred to as an enclosed layout transistor (ELT). In the context of hardening a complete neuron circuit against TID effects, together with the well-established ELT paradigm, it is possible to exploit the inclusion of other hardened devices, for instance, the memory element. In this sense, the Oxide-based Resistive Random Access Memory (OxRAM) can be used as the memory element, which is inherently tolerant against ionizing radiation and, hence, better suited for a fully hardened circuit. In this work, we propose to harden the design of an existing OxRAM-based neuron circuit through the inclusion of ELTs, i.e., to improve the radiation hardening characteristics of a preexistent convenient neuron circuit topology by using the enclosed gate geometry for the nMOS and pMOS devices. Electrical simulations, considering a standard commercial bulk CMOS fabrication process, in a 180-nm technology, have been carried out to validate our proposed design. In addition, we exploit two simulation setups: first, the OxRAM’s behavior in a simple circuit configuration, to provide a better understanding of the OxRAM device; second, the OxRAM-based neuron circuit, to evaluate the behavior of the proposed neuron circuit hardened with ELTs. The simulation results, supported by the analysis of former works regarding the incidence of ionizing radiation in OxRAM and ELTs, indicate that the proposed hardened neuron circuit is a feasible solution to embed neuromorphic computing in aerospace applications.

中文翻译：

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使用封闭式布局晶体管提高基于 CMOS OxRAM 的神经元电路的 TID 辐射鲁棒性


尽管航空航天应用具有出色的并行处理能力并降低了能耗，但它们仍然是嵌入人工神经网络的有吸引力的候选者。尽管如此，长期暴露于电离辐射的发生水平可能会降低其物理组件的性能，从而降低其可靠性和预期寿命。因此，在恶劣环境下运行之前，必须面对增强神经回路的辐射硬化特性的挑战。大幅减少电离辐射[称为总电离剂量 (TID)] 引起的长期杂散效应的一种可能解决方案是将传统的矩形 MOS 栅极几何形状更改为称为封闭式布局晶体管 (ELT) 的非标准拓扑。在针对 TID 效应强化完整神经元电路的背景下，结合完善的 ELT 范式，可以利用其他强化设备（例如存储元件）的包含性。从这个意义上说，基于氧化物的电阻式随机存取存储器（OxRAM）可以用作存储元件，它本质上能够耐受电离辐射，因此更适合完全硬化的电路。在这项工作中，我们建议通过包含 ELT 来强化现有的基于 OxRAM 的神经元电路的设计，即通过使用 nMOS 和 pMOS 的封闭栅极几何结构来改善现有方便的神经元电路拓扑的辐射强化特性设备。考虑到采用 180 nm 技术的标准商业批量 CMOS 制造工艺，已经进行了电气模拟，以验证我们提出的设计。 此外，我们还利用了两种仿真设置：首先，简单电路配置中的 OxRAM 行为，以更好地理解 OxRAM 器件；其次，基于 OxRAM 的神经元电路，用于评估所提出的使用 ELT 强化的神经元电路的行为。仿真结果得到了对 OxRAM 和 ELT 中电离辐射发生率的先前研究分析的支持，表明所提出的硬化神经元电路是将神经拟态计算嵌入航空航天应用的可行解决方案。