With increasing modulation order, a larger number of parallel source-series-terminated (SST) segments are required to implement precise feedforward equalization (FFE) tap-weight control in SST transmitters (TX). Due to the data routing complexity of the segmented structure, the dynamic power consumption of SST TX has become much more significant causing degradation in energy efficiency. This article presents a 32-Gb/s quarter-rate four-level pulse-amplitude modulation (PAM-4) SST TX with four-tap FFE implemented in 28-nm FDSOI CMOS technology using a high-impedance driver technique to decrease the gate loading of the data path of the SST TX. The output of the whole TX is kept matched to the standard characteristic impedance of the system even though the output impedance of the SST driver alone is high. The high-impedance driver technique decreases the total power consumption by 20% compared to the conventional design by providing a significant reduction in the capacitive load. Our measurement results show that the prototype TX consumes 77.9 mW and achieves an energy efficiency of 2.4 pJ/bit at a 32-Gb/s data rate for PAM-4 signaling.

中文翻译：

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具有四抽头 FFE 的 32 Gb/s PAM-4 SST 发射器，采用 28 纳米 FDSOI 中的高阻抗驱动器

随着调制阶数的增加，需要更多的并行源串联端接 (SST) 段来在 SST 发射机 (TX) 中实现精确的前馈均衡 (FFE) 抽头权重控制。由于分段结构的数据路由复杂性，SST TX 的动态功耗变得更加显着，导致能效下降。本文介绍了一种 32 Gb/s 四分之一速率四电平脉冲幅度调制 (PAM-4) SST TX，采用 28-nm FDSOI CMOS 技术实现四抽头 FFE，使用高阻抗驱动器技术来减少栅极加载 SST TX 的数据路径。即使单独 SST 驱动器的输出阻抗很高，整个 TX 的输出也保持与系统的标准特性阻抗匹配。与传统设计相比，高阻抗驱动器技术通过显着降低电容负载将总功耗降低了 20%。我们的测量结果表明，原型 TX 的功耗为 77.9 mW，在 PAM-4 信令的 32 Gb/s 数据速率下实现了 2.4 pJ/bit 的能效。