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Cross-Layer Approximate Hardware Synthesis for Runtime Configurable Accuracy
IEEE Transactions on Very Large Scale Integration (VLSI) Systems ( IF 2.8 ) Pub Date : 2021-04-01 , DOI: 10.1109/tvlsi.2021.3068312
Tanfer Alan , Andreas Gerstlauer , Jorg Henkel

Approximate computing trades off computation accuracy against energy efficiency. The extent of approximation tolerance, however, significantly varies with a change in input characteristics and applications. We propose a novel cross-layer approach for the synthesis of runtime accuracy-configurable hardware that minimizes energy consumption at area expense. To that end, first, we explore instantiating multiple hardware blocks in the architecture with different fixed approximation levels. These blocks can be selected dynamically and thus allow to configure the accuracy during runtime. They benefit from having fewer transistors and also synthesis relaxations in contrast to state-of-the-art gating mechanisms that only switch off a group of paths of the circuit. Our cross-layer approach combines instantiating such blocks in the architecture with area-efficient gating mechanisms that reduce toggling activity, creating a fine-grained design-time knob on energy versus area. We present a systematic methodology to explore this joint design space and find energy-area optimal solutions as a function of required accuracies, their utilization in the workload, together with hardware parameters: dynamic power savings, area of the hardware block, and leakage of the technology. Examining total energy savings for a range of circuits under different workloads and accuracy tolerances shows that our method finds Pareto-optimal solutions providing up to 32% and 60% energy savings compared to state-of-the-art accuracy-configurable gating mechanism and an exact hardware block, respectively, at 2× area cost.

中文翻译:


用于运行时可配置精度的跨层近似硬件综合



近似计算权衡计算精度和能源效率。然而,近似容差的范围随着输入特性和应用的变化而显着变化。我们提出了一种新颖的跨层方法来合成运行时精度可配置的硬件,以最大限度地减少面积消耗的能源消耗。为此,首先,我们探索在具有不同固定近似级别的架构中实例化多个硬件块。这些块可以动态选择,从而允许在运行时配置精度。与仅关闭电路的一组路径的最先进的门控机制相比,它们受益于更少的晶体管和综合松弛。我们的跨层方法将架构中的此类块实例化与面积高效的门控机制相结合,减少切换活动,从而在能量与面积之间创建细粒度的设计时旋钮。我们提出了一种系统的方法来探索这个联合设计空间,并根据所需的精度、其在工作负载中的利用率以及硬件参数(动态节能、硬件块的面积和泄漏)找到能量面积最佳解决方案。技术。检查不同工作负载和精度容差下一系列电路的总节能情况表明,我们的方法发现帕累托最优解决方案,与最先进的精度可配置门控机制和精确的硬件模块,分别以 2 倍的面积成本。
更新日期:2021-04-01
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