Vertical III-V nanowire MOSFETs show potential towards the ultimate transistor scaling. A high transconductance and current density are achieved based on the gate-all-around architecture. This work presents a high-frequency design of such devices, achieving more than 600 GHz cut-off frequencies (f T , f max ), at 20 nm gate length. Furthermore, capacitance design and scaling trends, supported by COMSOL Multiphysics simulations derive state-of-the-art parasitics magnitudes for vertical devices in general, reaching gate-drain capacitance values of 17 aF/wire, corresponding to 0.2 fF/μm. A unique co-designed feedback resonant circuit makes the device unilateral, exhibiting up to 15 dB gain in D-band at 0.5 V supply, and with a current density of 0.5 mA/μm. Finally, a 2-stage low noise amplifier is designed using an optimum matching concept to utilize the full available bandwidth. The resulting circuit performance is independent of transistor gate length, since any decrease in device intrinsic capacitance is assisted by an increase in device overlap capacitances in a setting unique to a current implementation of vertical nanowire MOSFETs. With this approach, amplifiers are designed with more than 20 dB gain and minimum noise figure of 2.5 dB in a simulation environment at 140 GHz. The proposed technology and design platform show a great potential in future low-power communication systems.

中文翻译：

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毫米波垂直 III-V 纳米线 MOSFET 器件到电路协同设计


垂直 III-V 纳米线 MOSFET 显示出实现最终晶体管尺寸缩小的潜力。基于环栅架构实现了高跨导和电流密度。这项工作提出了此类器件的高频设计，在 20 nm 栅极长度下实现了超过 600 GHz 的截止频率（f T 、 f max ）。此外，COMSOL Multiphysics 仿真支持的电容设计和缩放趋势通常得出垂直器件最先进的寄生量值，达到 17 aF/线的栅漏电容值，相当于 0.2 fF/μm。独特的共同设计的反馈谐振电路使该器件具有单边性，在 0.5 V 电源电压和 0.5 mA/μm 的电流密度下，在 D 频段中表现出高达 15 dB 的增益。最后，使用最佳匹配概念设计了一个 2 级低噪声放大器，以利用全部可用带宽。由此产生的电路性能与晶体管栅极长度无关，因为在当前垂直纳米线 MOSFET 实现所特有的设置中，器件本征电容的任何减小都会受到器件重叠电容的增加的帮助。通过这种方法，放大器的设计在 140 GHz 的模拟环境中具有超过 20 dB 的增益和 2.5 dB 的最小噪声系数。所提出的技术和设计平台在未来低功耗通信系统中显示出巨大的潜力。