A novel carrier-stored trench bipolar transistor (CSTBT) with heavily doped carrier-stored layer (CSL) is proposed and investigated by TCAD tools. The voltage of CSL is shielded by a buried p-type layer (P-bury) whose potential is clamped by a p-type Schottky Barrier Diode (pSBD) in series-connection with a PN diode. Hence, the CSL can be heavily doped, and the trade-off between on-state voltage drop (V_on) and turn-off loss (E_off) is substantially improved. Compared with that of a conventional CSTBT with floating P-base (FP-CSTBT), the E_off of the proposed CSTBT is reduced by 27.9% at V_on = 1.1 V. Owing to the shielding effect of the P-bury layer, the saturation current density of the proposed CSTBT is reduced by 52% compared with that of the FP-CSTBT. Consequently, significantly enlarged short-circuit safe operation area is obtained, and the short-circuit withstand time (t_sc) is increased to 12.8 s at ultra-low V_on (~ 1.1 V).

提出并通过 TCAD 工具研究了一种具有重掺杂载流子存储层 (CSL) 的新型载流子存储沟槽双极晶体管 (CSTBT)。CSL 的电压由埋入 p 型层 (P-bury) 屏蔽，其电位由与 PN 二极管串联的 p 型肖特基势垒二极管 (pSBD) 钳位。因此，CSL 可以被重掺杂，并且导通电压降 ( V _on ) 和关断损耗 ( E _off ) 之间的_权衡得到显着改善。与具有浮动 P 基极 (FP-CSTBT) 的传统 CSTBT 相比，所提出的 CSTBT的E _off在V _{on 时}降低了 27.9% = 1.1 V。由于 P 埋层的屏蔽效应，与 FP-CSTBT 相比，所提出的 CSTBT 的饱和电流密度降低了 52%。因此，获得了显着扩大的短路安全操作区，并且短路耐受时间 ( t _sc ) 在超低V _on (~1.1 V) 下增加到 12.8 s 。