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Evaluation of Single Event Upset Susceptibility of FinFET-based SRAMs with Weak Resistive Defects
Journal of Electronic Testing ( IF 0.9 ) Pub Date : 2021-06-01 , DOI: 10.1007/s10836-021-05949-x
Thiago Copetti , Guilherme Cardoso Medeiros , Mottaqiallah Taouil , Said Hamdioui , Letícia Bolzani Poehls , Tiago Balen

Fin Field-Effect Transistor (FinFET) technology enables the continuous downscaling of Integrated Circuits (ICs), using the Complementary Metal-Oxide Semiconductor (CMOS) technology in accordance with the More Moore domain. Despite demonstrating improvements on short channel effect and overcoming the growing leakage problem of planar CMOS technology, the continuity of feature size miniaturization tends to increase sensitivity to Single Event Upsets (SEUs) caused by ionizing particles, especially in blocks with higher transistor densities such as Static Random-Access Memories (SRAMs). Variation during the manufacturing process has introduced different types of defects that directly affect the SRAM's reliability, such as weak resistive defects. As some of these defects may cause dynamic faults, which require more than one consecutive operation to sensitize the fault at the logic level, traditional test approaches may fail to detect them, and test escapes may occur. These undetected faults, associated with weak resistive defects, may affect the FinFET-based SRAM reliability during its lifetime. In this context, this paper proposes to investigate the impact of ionizing particles on the reliability of FinFET-based SRAMs in the presence of weak resistive defects. Firstly, a TCAD model of a FinFET-based SRAM cell is proposed allowing the evaluation of the ionizing particle’s impact. Then, SPICE simulations are performed considering the current pulse parameters obtained with TCAD. In this step, weak resistive defects are injected into the FinFET-based SRAM cell. Results show that weak defects can positively or negatively influence the cell reliability against SEUs caused by ionizing particles.



中文翻译:

具有弱电阻缺陷的基于 FinFET 的 SRAM 的单事件翻转敏感性评估

鳍式场效应晶体管 (FinFET) 技术使用符合摩尔域的互补金属氧化物半导体 (CMOS) 技术,实现集成电路 (IC) 的持续缩小尺寸。尽管展示了短沟道效应的改进并克服了平面 CMOS 技术日益严重的泄漏问题,但特征尺寸小型化的连续性往往会增加对由电离粒子引起的单事件翻转 (SEU) 的敏感性,尤其是在具有更高晶体管密度的块中,例如静态随机存取存储器 (SRAM)。制造过程中的变化引入了直接影响 SRAM 可靠性的不同类型的缺陷,例如弱电阻缺陷。由于其中一些缺陷可能会导致动态故障,需要多次连续操作才能在逻辑级别敏感化故障,传统的测试方法可能无法检测到它们,并且可能会发生测试逃逸。这些未检测到的故障与弱电阻缺陷相关,可能会影响基于 FinFET 的 SRAM 在其生命周期内的可靠性。在此背景下,本文建议研究电离粒子在存在弱电阻缺陷的情况下对基于 FinFET 的 SRAM 可靠性的影响。首先,提出了基于 FinFET 的 SRAM 单元的 TCAD 模型,以评估电离粒子的影响。然后,考虑使用 TCAD 获得的电流脉冲参数进行 SPICE 模拟。在这一步中,弱电阻缺陷被注入到基于 FinFET 的 SRAM 单元中。

更新日期:2021-06-01
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