With the rapidly growing use of Convolutional Neural Networks (CNNs) in real-world applications related to machine learning and Artificial Intelligence (AI), several hardware accelerator designs for CNN inference and training have been proposed recently. In this paper, we present ATRIA, a novel bit-pArallel sTochastic aRithmetic based In-DRAM Accelerator for energy-efficient and high-speed inference of CNNs. ATRIA employs light-weight modifications in DRAM cell arrays to implement bit-parallel stochastic arithmetic based acceleration of multiply-accumulate (MAC) operations inside DRAM. ATRIA significantly improves the latency, throughput, and efficiency of processing CNN inferences by performing 16 MAC operations in only five consecutive memory operation cycles. We mapped the inference tasks of four benchmark CNNs on ATRIA to compare its performance with five state-of-the-art in-DRAM CNN accelerators from prior work. The results of our analysis show that ATRIA exhibits only 3.5% drop in CNN inference accuracy and still achieves improvements of up to 3.2x in frames-per-second (FPS) and up to 10x in efficiency (FPS/W/mm2), compared to the best-performing in-DRAM accelerator from prior work.

中文翻译：

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ATRIA：用于 In-DRAM CNN 处理的基于位并行随机算术的加速器

随着卷积神经网络 (CNN) 在与机器学习和人工智能 (AI) 相关的实际应用中的快速增长，最近提出了几种用于 CNN 推理和训练的硬件加速器设计。在本文中，我们提出了 ATRIA，这是一种新型的基于位并行随机算法的 In-DRAM 加速器，用于 CNN 的节能和高速推理。ATRIA 在 DRAM 单元阵列中采用轻量级修改来实现基于位并行随机算法的 DRAM 内乘法累加 (MAC) 操作的加速。ATRIA 通过仅在五个连续的内存操作周期内执行 16 次 MAC 操作，显着提高了处理 CNN 推理的延迟、吞吐量和效率。我们将四个基准 CNN 的推理任务映射到 ATRIA 上，以将其性能与先前工作中的五个最先进的 in-DRAM CNN 加速器进行比较。我们的分析结果表明，相比之下，ATRIA 的 CNN 推理精度仅下降了 3.5%，并且仍然实现了高达 3.2 倍的每秒帧数 (FPS) 和高达 10 倍的效率 (FPS/W/mm2) 的改进到先前工作中性能最佳的 DRAM 加速器。