Field-programmable gate array (FPGA)-based ternary content-addressable memories (TCAMs) are constantly evolving in terms of hardware, power consumption, and speed. One disadvantage of these emulated TCAMs is its poor update-latency. Traditional FPGA-based TCAMs have an update-latency of ${N}$ clock cycles compared to the lookup-latency of one clock cycle, where ${N}$ is the depth of TCAM. Later, the update-latency is improved to ${t}$ clock cycles, where ${t}$ is the number of don’t care bits. In this letter, we presented two mechanisms for updating FPGA-based TCAM and successfully implemented on Xilinx Virtex-6 FPGA: an accelerated MUX-Update mechanism and a cost-effective LUT-Update mechanism. MUX-Update provides an update-latency of ${W}+1$ clock cycles by using only three input/output (I/O) pins, whereas ${W}$ is the width of TCAM. LUT-Update yields a constant update-latency of 2 clock cycles, independent of the size of TCAM, by using ${W}$ I/O pins.

中文翻译：

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基于 FPGA 的三元内容可寻址存储器的加速更新机制

基于现场可编程门阵列 (FPGA) 的三元内容可寻址存储器 (TCAM) 在硬件、功耗和速度方面不断发展。这些仿真的TCAM的缺点之一是更新延迟慢。传统的基于 FPGA 的 TCAM 的更新延迟为 $ {N} $ 时钟周期与一个时钟周期的查找延迟之间的比较，其中 $ {N} $ 是 TCAM 的深度。后来，更新延迟改进为 ${t}$ 时钟周期，其中 ${t}$ 是无关位的数量。在这封信中，我们介绍了两种更新基于 FPGA 的 TCAM 并在 Xilinx Virtex-6 FPGA 上成功实施的机制：加速 MUX-Update 机制和经济高效的 LUT-Update 机制。MUX-Update 提供的更新延迟为 ${W}+1$ 仅使用三个输入/输出 (I/O) 引脚的时钟周期，而 ${W}$ 是 TCAM 的宽度。LUT-Update 产生 2 个时钟周期的恒定更新延迟，与 TCAM 的大小无关，通过使用 ${W}$ I / O引脚。