In this article, the impact of random fluctuation sources, such as metal gate granularity (MGG), line edge roughness (LER), and random dopant fluctuations (RDFs), are numerically studied for U-shaped n-channel fully depleted silicon on insulator (FDSOI) MOSFET (U-SOIFET) over conventional n-channel FDSOI MOSFET (C-SOIFET) for 7-nm technology node. This article reports that improved short-channel effect immunity in U-SOIFET results in less $1\sigma $ threshold voltage ( ${V}_{T}$ ) and ON-current ( ${I}_{ \mathrm{\scriptscriptstyle ON}}$ ) fluctuations compared to C-SOIFET due to MGG and LER variability sources. U-SOIFET exhibits a low ${V}_{T}$ mismatch index ( ${A}_{\Delta VT}=1.78$ mV. $\mu \text{m}$ ) close to the literature reported. Due to combined variability sources, U-SOIFET shows less ${V}_{T}$ , ${I}_{ \mathrm{\scriptscriptstyle ON}}$ , subthreshold swing (SS), and DIBL fluctuations compared to C-SOIFET. Immunity to statistical variability sources makes U-SOIFET a suitable silicon on insulator (SOI) device architecture for future CMOS logic device applications.

中文翻译：

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基于 TCAD 对低于 7 纳米技术的 U 通道 FDSOI n-MOSFET 统计变异性抗扰度的研究


本文数值研究了随机波动源（例如金属栅极粒度（MGG）、线边缘粗糙度（LER）和随机掺杂波动（RDF））对绝缘体上 U 形 n 沟道全耗尽硅的影响(FDSOI) MOSFET (U-SOIFET) 优于传统 n 沟道 FDSOI MOSFET (C-SOIFET)，适用于 7 纳米技术节点。本文报告了 U-SOIFET 中短沟道效应抗扰度的改进导致 $1\sigma $ 阈值电压 ( ${V}_{T}$ ) 和导通电流 ( ${I}_{ \mathrm{\scriptscriptstyle ON}}$ ) 与 C-SOIFET 相比，由于 MGG 和 LER 变异源而存在波动。 U-SOIFET 表现出较低的 ${V}_{T}$ 失配指数 ( ${A}_{\Delta VT}=1.78$ mV. $\mu \text{m}$ )，接近文献报道。由于组合的可变性源，与 C-相比，U-SOIFET 显示出更少的 ${V}_{T}$ 、 ${I}_{ \mathrm{\scriptscriptstyle ON}}$ 、亚阈值摆幅 (SS) 和 DIBL 波动索菲特。不受统计变异性源的影响，使 U-SOIFET 成为适合未来 CMOS 逻辑器件应用的绝缘体上硅 (SOI) 器件架构。