The influence of hot-carrier degradation (HCD) on lateral trap distribution within the device channel is experimentally investigated for gate-all-around nanowire (NW) nFETs. In particular, using drain-induced barrier lowering (DIBL) as the parameter, the damage caused by hot-carriers (HCs) is monitored for devices with different geometries, including fin width and gate length. It is observed that with the change in NW width, different degrading mechanisms alter the trap distribution during the application of hot-carrier stress. The trap distribution profile which is found to peak at the drain for very narrow NWs gradually turns uniform as width increases. Interestingly, the carrier location and localization remain the same irrespective of the gate lengths of the NWs. In order to understand the implications of device scaling on HC reliability of advanced CMOS devices, the relative contribution of degradation caused by single and multi carriers degradation process is studied. Both the mechanisms are shown to significantly affect the HC damage profile by causing either highly localized or uniform damage along the device channel.

中文翻译：

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热载流子应力期间环栅纳米线 MOSFET 中 DIBL 的时间演化


针对环栅纳米线 (NW) nFET，我们通过实验研究了热载流子退化 (HCD) 对器件沟道内横向陷阱分布的影响。特别是，使用漏极诱导势垒降低（DIBL）作为参数，可以监测具有不同几何形状（包括鳍片宽度和栅极长度）的器件由热载流子（HC）引起的损坏。据观察，随着纳米线宽度的变化，在施加热载流子应力期间，不同的降解机制改变了陷阱分布。对于非常窄的纳米线，陷阱分布轮廓在漏极处达到峰值，随着宽度的增加逐渐变得均匀。有趣的是，无论纳米线的栅极长度如何，载流子位置和定位都保持相同。为了了解器件尺寸缩小对先进 CMOS 器件 HC 可靠性的影响，研究了单载流子和多载流子退化过程引起的退化的相对贡献。这两种机制都显示出通过沿着器件通道引起高度局部化或均匀的损伤来显着影响 HC 损伤曲线。