A physics-based compact model of reliability degradation in analog resistive random access memory (RRAM) is developed. The model captures the stochastic degradation behaviors of retention, bit yield, and endurance during analog resistive switching. The model is verified with statistical data measured from analog RRAM arrays. Based on this compact model, a device-to-system simulation framework for the computation-in-memory (CIM) system is developed. This simulation framework is a silicon-verified versatile simulator that supports both inference and training, and fully considers the device nonideal effects and circuit constraints. Based on the reliability evaluation results, optimization guidelines to suppress the impact of device reliability degradation are proposed. This work provides a useful device-system codesign tool for developing large-scale CIM systems with high performance.

中文翻译：

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用于内存计算设备到系统协同设计和基准测试的模拟 RRAM 紧凑可靠性模型


开发了一种基于物理的模拟电阻随机存取存储器 (RRAM) 可靠性退化的紧凑模型。该模型捕获模拟电阻开关过程中保留率、比特率和耐用性的随机退化行为。该模型通过模拟 RRAM 阵列测量的统计数据进行了验证。基于这个紧凑模型，开发了内存计算（CIM）系统的设备到系统仿真框架。该仿真框架是经过硅验证的多功能模拟器，支持推理和训练，并充分考虑器件非理想效应和电路约束。根据可靠性评估结果，提出抑制器件可靠性下降影响的优化指南。这项工作为开发高性能的大规模 CIM 系统提供了一个有用的设备系统协同设计工具。