The full well capacity (FWC) and the pinned photodiode (PPD) capacitance of four-transistor pixel in a CMOS image sensor are reported to be dependent on the potential barrier offered by transfer gate (TG). The asymmetrical TG channel potential increases the effective potential barrier, thereby increasing the FWC and decreasing the feedforward charges. At the PPD-TG interface, a potential pocket can exist, the influence of which is minimized to lower the image lag. In the presence of a potential pocket, two charge transfer potential barriers (CTPBs) are present in the charge transfer path. The combined effect of the two potential barriers is higher than the single barrier reported in the literature. The CTPB depends on the number of integrated PPD charges and influences the FWC and PPD capacitance. The improved PPD capacitance model matches well with the measurement results when the influence of potential pocket on CTPB is considered.

中文翻译：

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CMOS图像传感器钉扎光电二极管中电荷转移势垒分析


据报道，CMOS 图像传感器中四晶体管像素的全阱电容 (FWC) 和钉扎光电二极管 (PPD) 电容取决于传输门 (TG) 提供的势垒。不对称的TG沟道电势增加了有效势垒，从而增加了FWC并减少了前馈电荷。在 PPD-TG 界面处，可能存在潜在的口袋，其影响被最小化以降低图像延迟。在存在电势袋的情况下，电荷传输路径中存在两个电荷传输势垒 (CTPB)。两种潜在屏障的综合效应高于文献报道的单一屏障。 CTPB 取决于集成 PPD 电荷的数量并影响 FWC 和 PPD 电容。当考虑电势袋对CTPB的影响时，改进的PPD电容模型与测量结果吻合良好。