High-level synthesis (HLS) tools generate hardware designs from high-level programming languages and should liberate designers from the details of hardware description languages like VHDL and Verilog. HLS tools typically build datapaths that are controlled using a centralized controller, which relies on a compile-time schedule to determine the clock cycle when each operation executes. Such an approach results in high-throughput pipelined designs only in cases where memory accesses are provably independent and critical control decisions are determinable during code compilation. Unfortunately, when this is not the case, current tools must make pessimistic assumptions, yielding inferior schedules and lower performance. Recent advances in HLS have explored methods to overcome the conservatism in static scheduling and to remove the inability of HLS tools to handle dynamic events. Dataflow circuits play a significant role in this context: they are built out of units that communicate using point-to-point pairs of handshake control signals and this distributed control mechanism effectively implements a dynamic schedule, adapted at runtime to particular memory and control outcomes. Dataflow circuits can exploit the same optimization opportunities as standard HLS circuits (i.e., pipelining and resource sharing), but also introduce to HLS features similar to those of modern superscalar processors (i.e., out-of-order memory accesses and speculative execution), which are key for HLS to be successful in new contexts and broader application domains.

中文翻译：

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将通用代码合成到动态调度电路中


高级综合 (HLS) 工具可通过高级编程语言生成硬件设计，并将设计人员从 VHDL 和 Verilog 等硬件描述语言的细节中解放出来。 HLS 工具通常构建使用集中控制器控制的数据路径，该控制器依赖编译时调度来确定每个操作执行时的时钟周期。仅在内存访问可证明是独立的并且关键控制决策在代码编译期间可确定的情况下，这种方法才会产生高吞吐量流水线设计。不幸的是，如果情况并非如此，当前的工具必须做出悲观的假设，从而产生较差的时间表和较低的性能。 HLS 的最新进展探索了克服静态调度中的保守性并消除 HLS 工具无法处理动态事件的方法。数据流电路在这种情况下发挥着重要作用：它们是由使用点对点握手控制信号对进行通信的单元构建的，这种分布式控制机制有效地实现了动态调度，在运行时适应特定的内存和控制结果。数据流电路可以利用与标准 HLS 电路相同的优化机会（即流水线和资源共享），而且还引入类似于现代超标量处理器的 HLS 功能（即乱序内存访问和推测执行），这是 HLS 在新环境和更广泛的应用领域取得成功的关键。