Radar Digital Receiver (RDR) requires to perform many computationally intensive operations in real-time. Therefore, RDRs have been implemented using DSP (Digital Signal Processor) or high performance FPGA (Field Programmable Gate Array) based customized hardware and software, and optimized for heavy math computation. These designs have a few limitations like long development cycle and high implementation cost due to customized hardware and proprietary software including development tools, Board Support Package and Operating System (OS). A new design is proposed to overcome these limitations by making use of low-cost COTS (Commercially Off The Shelf) hardware containing multi-core processors that are enabled to perform complex math efficiently, open source software and ready to use Intel’s IPP (Integrated Performance Primitives) library of functions. A prototype RDR for tracking application is developed and evaluated by integrating with an S-Band Radar and tracking various targets. The details of design, implementation and performance evaluation of the prototype RDR are presented in this paper.

雷达数字接收器 (RDR) 需要实时执行许多计算密集型操作。因此，RDR 已使用基于 DSP（数字信号处理器）或高性能 FPGA（现场可编程门阵列）的定制硬件和软件来实现，并针对繁重的数学计算进行了优化。由于定制硬件和专有软件（包括开发工具、板级支持包和操作系统 (OS)），这些设计存在一些限制，例如开发周期长和实施成本高。提出了一种新设计，通过使用包含多核处理器的低成本 COTS（商业现货）硬件来克服这些限制，这些处理器能够有效地执行复杂的数学运算，开源软件并准备使用英特尔的 IPP（集成性能基元）函数库。通过与 S 波段雷达集成并跟踪各种目标，开发和评估了用于跟踪应用的原型 RDR。本文详细介绍了原型 RDR 的设计、实现和性能评估。