This article presents a 3-D reconfigurable memory I/O transceiver using a quad-band interconnect (QBI). The 3-D QBI provides I/O data reconfigurability, decreases latency, and reduces pin count for future compact mobile memory interfaces. The 3-D integrated circuit (3-D IC) technique is utilized to reduce signal latency and improve signal integrity. A novel quad-band transformer is proposed to achieve reconfigurable four-band data communication and reduce the I/O pin count by four times. A two-tier QBI die-stack is implemented to verify the QBI design. Face-to-face configuration with μbump interconnects is used to save cost. The QBI chips are designed and fabricated in a 180-nm CMOS process. The chip areas of the top and bottom dies are 1.77 and 1.4 mm 2 , respectively. The measured data rates, with bit error rate (BER) <; 10 -15 , are up to 2 Gb/s in the baseband (BB) and 2.3, 2.5, and 3 Gb/s in RF-bands. The QBI energy efficiencies, with a 1.8-V supply voltage, are 5.9 pJ/b in the BB and 6.2, 7.4, and 8 pJ/b in the RF-bands.

中文翻译：

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使用四频带互连的 3D 可重构存储器 I/O 接口


本文介绍了一种使用四频互连 (QBI) 的 3D 可重配置存储器 I/O 收发器。 3-D QBI 提供 I/O 数据可重新配置性，减少延迟，并减少未来紧凑型移动存储器接口的引脚数。利用 3D 集成电路 (3-D IC) 技术来减少信号延迟并提高信号完整性。提出了一种新颖的四频带变压器来实现可重新配置的四频带数据通信并将I/O引脚数减少四倍。实施两层 QBI 芯片堆栈来验证 QBI 设计。采用具有μbump互连的面对面配置来节省成本。 QBI 芯片采用 180 nm CMOS 工艺设计和制造。顶部和底部芯片的芯片面积分别为1.77 和1.4 mm 2 。测得的数据速率，误码率 (BER) <； 10 -15 ，基带 (BB) 高达 2 Gb/s，RF 频段高达 2.3、2.5 和 3 Gb/s。电源电压为 1.8V 时，QBI 的能效在 BB 频段为 5.9 pJ/b，在 RF 频段为 6.2、7.4 和 8 pJ/b。