Recent advances in wire-like communication channels without a physical wire has seen the emergence of wireline-like broadband channels but with atypical high loss. Communication links using such channels (e.g., Proximity Communication, Human Body Communication) are typically broadband, like wireline systems but noise-limited like wireless systems. Hence, employing broad-band communication through such emerging channels calls for new research on analyzing, designing and finding the theoretical limits for receiver topologies suitable for lossy broad-band channels. In this paper, we present a theoretical analysis framework for various broadband receivers in combination with low-noise amplifiers and proposed multi-integrator cascade, which provides significant gain with relatively lower power consumption than the standard gain elements. Through 1) derivation of new noise analysis of integrating-sampling receivers, 2) proposal of a new circuit topology (multi-integrating receiver, MIR) and 3) development of a thorough design space exploration framework, including use of a combination of wireless-inspired Low-noise amplifiers (LNA) with wireline-inspired strong-ARM latches, and the newly proposed MIRs, this paper demonstrates the optimum design choices for some common scenarios. Maximum achievable data rate and optimum energy-efficiency for various channel losses have been obtained theoretically for different topologies revealing their advantages and limitations, intended to serve as a guide for future receiver designs for lossy broad-band channels. All the circuits have been designed in 65 nm CMOS process with a 1 V supply voltage.

中文翻译：

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有损宽带通道多集成 RX 前端的理论分析


没有物理线路的类有线通信信道的最新进展已经出现了类有线宽带信道，但具有非典型的高损耗。使用此类信道的通信链路（例如，接近通信、人体通信）通常是宽带的，如有线系统，但噪声受限，如无线系统。因此，通过此类新兴信道采用宽带通信需要对适合有损宽带信道的接收器拓扑进行分析、设计和寻找理论极限的新研究。在本文中，我们提出了各种宽带接收器与低噪声放大器相结合的理论分析框架，并提出了多积分器级联，与标准增益元件相比，它以相对较低的功耗提供了显着的增益。通过 1) 推导积分采样接收器的新噪声分析，2) 提出新的电路拓扑（多积分接收器，MIR），以及 3) 开发彻底的设计空间探索框架，包括使用无线-受有线启发的强 ARM 锁存器的低噪声放大器 (LNA) 的启发，以及新提出的 MIR，本文演示了一些常见场景的最佳设计选择。对于不同的拓扑结构，理论上可以获得最大可实现的数据速率和针对各种通道损耗的最佳能效，揭示了它们的优点和局限性，旨在为未来有损宽带通道的接收机设计提供指导。所有电路均采用 65 nm CMOS 工艺设计，电源电压为 1 V。