This paper systematically studies the reliability of non-uniformly doped Double Gate Junctionless transistor using ATLAS TCAD simulation. The reliability analysis is mainly based on the understanding of Band-To-Band-Tunneling (BTBT) current, lattice temperature, drain conductance and gate leakage current. Presented results show that higher source/drain work-function is beneficial in reducing tunneling current (1 × 10⁻⁹ A to 4 × 10⁻¹¹ A @ V_gs= −1 V) but eventually it will also degrade electrostatic current significantly (∼3 order). Source/Drain length has also been varied during optimization and it has been observed that, shorter source drain extension region degrades the device reliability (i.e. higher magnitude of tunneling current (7 × 10⁻⁹ A @ V_gs=−1 V for L_S= L_D= 5 nm)). Different doping profile considered for performance assessment are: uniform, step (i.e. low–low–high and high–high–low etc.) and different configurations of gaussian doping profile. Minimum variation in tunneling current with negative gate bias, i.e. ∼ 1 order has been seen from the device having uniform doping 10¹⁹ cm⁻³ but at the cost of significantly high off-state current (2 × 10⁻⁹ A @ V_gs= 0 V) and tunneling current (2 × 10⁻⁸ A @ V_gs= −1 V). Thus, instead of using uniform doping, step type profile (i.e. Case A) is the better choice which results in lower tunneling current (1 × 10⁻⁹ A @ V_gs= −1 V), moderate lattice temperature (326) and better I_on/I_off ratio (243 × 10⁸). Device lattice temperature has also been controlled by using step A doping profile even at the higher operating temperatures due to lower Self Heating Effect.

本文利用ATLAS TCAD仿真系统研究了非均匀掺杂双栅无结晶体管的可靠性。可靠性分析主要基于对带对带隧道（BTBT）电流、晶格温度、漏极电导和栅极漏电流的理解。呈现的结果表明，较高的源极/漏极功函数有利于降低隧道电流（1 × 10 ^-9  A 至 4 × 10 ^-11  A @ V _gs = −1 V），但最终它也会显着降低静电电流（~ 3阶）。源极/漏极长度在优化过程中也发生了变化，并且已经观察到，较短的源极漏极扩展区会降低器件的可靠性（即更高幅度的隧道电流（7 × 10 ⁻⁹  A @ V _gs = −1 V for L _S =  L _D = 5 nm））。性能评估考虑的不同掺杂分布是：均匀、阶梯（即低-低-高和高-高-低等）和高斯掺杂分布的不同配置。从具有均匀掺杂 10 ¹⁹  cm ^-3的器件中可以看出负栅极偏置下隧道电流的最小变化，即∼ 1 阶，但代价是显着高的断态电流（2 × 10 ^-9  A @ V _gs= 0 V) 和隧道电流 (2 × 10 ⁻⁸  A @ V _gs = −1 V)。因此，不是使用均匀掺杂，阶梯型分布（即案例 A）是更好的选择，它会导致较低的隧道电流（1 × 10 ^-9  A @ V _gs = -1 V）、适中的晶格温度 (326) 和更好的效果I _on / I _off比率 (243 × 10 ⁸ )。由于较低的自热效应，即使在较高的工作温度下，也可以通过使用步骤 A 掺杂分布来控制器件晶格温度。