The work describes the new architecture of a fixed-point arithmetic unit. It is based on the use of integer arithmetic operations for which the information about the scale of the processed numbers is contained in the binary code of the arithmetic instruction being executed. Therefore, this approach is different from the typical way of implementing fixed-point operations on standard processors. The presented solution is also significantly different from the one used in floating-point arithmetic, as the decision to determine the appropriate scale is made at the stage of compiling the code and not during its execution. As a result, the real-time processing of real numbers is simplified and, therefore, faster. The described method provides a better ratio of the processing efficiency to the complexity of the digital system than other methods. In particular, the advantage of using the described method in FPGA-based embedded control systems should be indicated. Experimental tests on an industrial servo-drive confirm the correctness of the described solution.

中文翻译：

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具有基于FPGA的嵌入式系统缩放机制的定点算术单元

该工作描述了定点算术单元的新体系结构。它基于整数运算的使用，对于该整数运算，有关已处理数字的小数位数的信息包含在正在执行的算术指令的二进制代码中。因此，此方法不同于在标准处理器上实现定点运算的典型方法。所提出的解决方案也与浮点算术中使用的解决方案有很大不同，因为确定适当比例的决定是在编译代码的阶段而不是在代码执行期间进行的。结果，简化了实数的实时处理，因此更快。所描述的方法提供了比其他方法更好的处理效率与数字系统的复杂性的比率。尤其应指出在基于FPGA的嵌入式控制系统中使用所述方法的优势。在工业伺服驱动器上的实验测试证实了上述解决方案的正确性。