In this paper, we propose a low-complexity and high-speed VLSI architecture design methodology for complex square root computation using COordinate Rotation DIgital Computer (CORDIC). The proposed methodology is independent of angle computation in the CORDIC unlike the state-of-the-art methodologies. The proposed methodology is modelled in VHDL and synthesized under the TSMC 45-nm CMOS technology @ 1 GHz frequency. The synthesis results show that the proposed design saves 18.39%, 4.06% and 17.26%, 2.56% on chip area and power consumption when compared with the state-of-the-art methodologies without loss in accuracy. The proposed design saves the latency of 16 and 14 clock cycles when compared with the state-of-the-art implementations. The proposed design can process 23.4 and 127.344 billion additional samples per one joule energy when compared with the state-of-the-art designs.

在本文中，我们提出了一种使用坐标旋转数字计算机（CORDIC）进行复杂平方根计算的低复杂度和高速VLSI架构设计方法。与最新方法不同，所提出的方法与CORDIC中的角度计算无关。所提出的方法在VHDL中建模，并在1 GHz频率的TSMC 45纳米CMOS技术下进行了合成。综合结果表明，与最新的方法相比，所提出的设计节省了芯片面积和功耗的18.39％，4.06％和17.26％，2.56％。与最新的实现方案相比，所提出的设计节省了16和14个时钟周期的延迟。拟议的设计可以处理23.4和127。