We propose a second-order $RC$ -only voltage-mode active all-pass filter (APF) as an analog time-delay cell. The core circuit of the proposed APF is canonical and consists of only one transistor, one resistor, and two capacitors. Therefore, this design is area efficient, and it is suitable for low-gigahertz frequency applications, where conventional $LC$ designs are not practical, due to large inductor sizes. The APF design equations are derived and the circuit noise and sources of nonideality are discussed. The proposed 65-nm CMOS APF is experimentally verified to demonstrate a wideband range of 0.4–2 GHz and a continuously tunable delay in the range of 30–57 ps with an rms delay variation error <1.42 ps. The gain variation is below 0.75 dB for all delay settings over the bandwidth. The circuit occupies only $1870~\mu \text {m}^{2}$ while drawing 2.47 mA from a 1-V supply.

中文翻译：

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延迟可调紧凑型 钢筋混凝土-仅全通滤波器

我们建议二阶 $ RC $ 仅电压模式有源全通滤波器（APF）作为模拟延时单元。提出的APF的核心电路是规范的，仅由一个晶体管，一个电阻和两个电容器组成。因此，该设计具有较高的面积利用率，适用于常规情况下的低千兆赫兹频率应用 $ LC $ 由于电感尺寸较大，这种设计不切实际。推导了APF设计方程，并讨论了电路噪声和非理想源。提议的65 nm CMOS APF经过实验验证，可显示0.4–2 GHz的宽带范围和30–57 ps范围内的连续可调延迟，且均方根延迟变化误差<1.42 ps。对于整个带宽上的所有延迟设置，增益变化均低于0.75 dB。该电路仅占用 $ 1870〜\ mu \ text {m} ^ {2} $ 从1V电源汲取2.47 mA电流时。