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A New Tunable SISO Filter Designed in 40nm CMOS for Bilateral Inverse and Buffer Filtering Applications
Journal of Circuits, Systems and Computers ( IF 0.9 ) Pub Date : 2021-05-11 , DOI: 10.1142/s0218126621502406
Umar Mohammad 1 , Fang Tang 1 , Shu Zhou 1 , Mohd Yusuf Yasin 2
Affiliation  

A new study imitating the design and implementation of single-input–single-output (SISO) filters as bilateral filters has been presented in this paper. Second generation current controlled current conveyor (CCCII), being a popular low power active element was considered for the realization of the proposed design. Complete design, analysis and implementation of the voltage mode SISO filter was done using only two CCCII’s and two passive parasitic components. The striking feature of this work is that the proposed design can be made to work at either the input node or the output node, as well as in the cases; the change of direction changes the filter into an inverse filter and buffer filter. Basic filter applications like low-pass, high-pass, band-pass and band-stop were aimed to check the uniformity of the proposed design at different frequencies. Results perceived from the simulation study were fare enough on both the side nodes of the proposed design. Categorically, the circuit can be aimed to work in lieu of a filter transceiver. The consistency of the circuit was analyzed by the nodal analysis. Whereas the working performance was enormously analyzed and evaluated during the simulation analysis. The proposed design was simulated in HSPICE tool to exhibit and exploit the delivery, using the 45nm predictive technology model (PTM) parameters, with ±1V rail to rail voltages. Maximum power consumption of the circuit is around 138.5μW. Finally, the design was also implemented in Cadence Virtuoso using 40nm SMIC parameters.

中文翻译:

一种采用 40nm CMOS 设计的新型可调谐 SISO 滤波器,用于双边反向和缓冲滤波应用

本文提出了一项模拟单输入单输出 (SISO) 滤波器作为双边滤波器的设计和实现的新研究。第二代电流控制电流传输器 (CCCII) 是一种流行的低功率有源元件,被考虑用于实现所提出的设计。仅使用两个 CCCII 和两个无源寄生元件就完成了电压模式 SISO 滤波器的完整设计、分析和实施。这项工作的显着特点是,所提出的设计可以在输入节点或输出节点以及案例中工作;方向的改变将滤波器变为逆滤波器和缓冲滤波器。低通、高通、带通和带阻等基本滤波器应用旨在检查所提议设计在不同频率下的一致性。从模拟研究中感知到的结果在提议的设计的两个侧节点上都足够了。明确地说,该电路可以代替滤波器收发器工作。采用节点分析法分析电路的一致性。而在模拟分析过程中,对工作性能进行了大量分析和评估。建议的设计在 HSPICE 工具中进行了模拟,以展示和利用交付,使用 45nm 预测技术模型 (PTM) 参数,具有±1V 轨到轨电压。电路最大功耗为138.5左右μW. 最后,该设计也在 Cadence Virtuoso 中实现,使用 40纳米中芯国际参数。
更新日期:2021-05-11
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