Covert Hardware Trojan Horses (HTH) introduced by malicious attackers during the fabless manufacturing process of integrated circuits (IC) have the potential to cause malignant functions within the circuit. This article employs a Design-for-Security technique to detect any HTHs present in the circuit by inserting tri-state buffers (TSB) in the ICs that inject the internal nets with weighted logic values during the test phase. This increases the transitions in the logic values of the nets within the IC, thereby stimulating any inserted HTH circuits. The TSBs are efficiently inserted in the IC considering various circuit parameters and testability measures to bolster the transitions in logic values of the nets throughout the IC while minimising the area overhead. Simulation results show a significant increase in transitions in logic values within HTH triggers using this method, thus aiding in their detection through side-channel analysis or direct activation of the payload.

中文翻译：

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通过改进休眠网络的切换来检测硬件木马

恶意攻击者在集成电路 (IC) 的无晶圆制造过程中引入的隐蔽硬件特洛伊木马 (HTH) 有可能导致电路内出现恶性功能。本文采用安全设计技术来检测电路中存在的任何 HTH，方法是在 IC 中插入三态缓冲器 (TSB)，在测试阶段向内部网络注入加权逻辑值。这增加了 IC 内网络逻辑值的转换，从而刺激任何插入的 HTH 电路。考虑到各种电路参数和可测试性措施，TSB 被有效地插入 IC 中，以支持整个 IC 网络的逻辑值转换，同时最大限度地减少面积开销。