Logic locking is a hardware security technique aimed at protecting intellectual property against security threats in the IC supply chain, especially those posed by untrusted fabrication facilities. Such techniques incorporate additional locking circuitry within an integrated circuit (IC) that induces incorrect digital functionality when an incorrect verification key is provided by a user. The amount of error induced by an incorrect key is known as the effectiveness of the locking technique. A family of attacks known as “SAT attacks” provide a strong mathematical formulation to find the correct key of locked circuits. To achieve high SAT resilience (i.e., complexity of SAT attacks), many conventional logic locking schemes fail to inject sufficient error into the circuit when the key is incorrect. For example, in the case of SARLock and Anti-SAT, there are usually very few (or only one) input minterms that cause any error at the circuit output. The state-of-the-art s tripped functionality logic locking (SFLL) technique provides a wide spectrum of configurations that introduced a tradeoff between SAT resilience and effectiveness. In this work, we prove that such a tradeoff is universal among all logic locking techniques. To attain high effectiveness of locking without compromising SAT resilience, we propose a novel logic locking scheme, called Strong Anti-SAT (SAS). In addition to SAT attacks, removal-based attacks are another popular kind of attack formulation against logic locking where the attacker tries to identify and remove the locking structure. Based on SAS, we also propose Robust SAS (RSAS) that is resilient to removal attacks and maintains the same SAT resilience and effectiveness as SAS. SAS and RSAS have the following significant improvements over existing techniques. (1) We prove that the SAT resilience of SAS and RSAS against SAT attack is not compromised by increase in effectiveness . (2) In contrast to prior work that focused solely on the circuit-level locking impact, we integrate SAS-locked modules into an 80386 processor and show that SAS has a high application-level impact. (3) Our experiments show that SAS and RSAS exhibit better SAT resilience than SFLL and their effectiveness is similar to SFLL.

中文翻译：

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具有高应用级影响的强大且具有攻击弹性的逻辑锁定

逻辑锁定是一种硬件安全技术，旨在保护知识产权免受 IC ​​供应链中的安全威胁，尤其是不受信任的制造设施造成的威胁。这样的技术在集成电路(IC)内结合了额外的锁定电路，当用户提供不正确的验证密钥时，该集成电路会引发不正确的数字功能。由不正确的密钥引起的错误量称为效力的锁定技术。一系列被称为“SAT 攻击”的攻击提供了一个强大的数学公式来找到锁定电路的正确密钥。为了达到高SAT弹性（即 SAT 攻击的复杂性），许多传统的逻辑锁定方案在密钥不正确时无法向电路注入足够的错误。例如，在 SARLock 和 Anti-SAT 的情况下，通常很少（或只有一个）输入最小项会导致电路输出出现任何错误。最先进的s触发功能逻辑锁定 (SFLL) 技术提供了广泛的配置，在 SAT 弹性和有效性之间进行了权衡。在这项工作中，我们证明了这种权衡在所有逻辑锁定技术中是普遍的。为了在不影响 SAT 弹性的情况下获得高效的锁定，我们提出了一种新的逻辑锁定方案，称为强反 SAT (SAS)。除了 SAT 攻击，基于移除的攻击是另一种流行的针对逻辑锁定的攻击公式，攻击者试图识别并移除锁定结构。在 SAS 的基础上，我们还提出了 Robust SAS (RSAS)，它对移除攻击具有弹性并保持相同SAT弹性和效力作为SAS。SAS 和 RSAS 对现有技术有以下重大改进。(1) 我们证明SAT弹性SAS 和 RSAS 对 SAT 攻击的影响不会因增加效力. (2) 与之前仅关注电路级锁定影响的工作相比，我们将 SAS 锁定模块集成到 80386 处理器中，并表明 SAS 具有很高的应用级影响。(3) 我们的实验表明，SAS 和 RSAS 表现出比 SFLL 更好的 SAT 弹性，并且它们的有效性与 SFLL 相似。