Digital Signal Processing (DSP) is a very significant and active research area. High throughput is a requirement for most wireless communication systems. The critical bottleneck that affects communication ability is the Fast Fourier Transform (FFT), which is the essence of most modulators. Currently, Floating point FFT processors have been used in Radar signal processing, fast convolution, Spectrum estimation and OFDM based modulators/demodulators. Efficient VLSI based architectures are required for real-time FFT processing. The multiplication limits the performance in terms of throughput of FFT. Consequently, there is a need for high speed and low power multiplier architectures with minor truncation error. The present paper presents a modified binary floating-point multiplier using Vedic mathematics and a modification in the previously published Vedic multiplier circuit has been proposed. The entire design has been implemented in Verilog HDL. Synthesis and simulations are done using Xilinx ISE Design Suite 14.5.The performance evaluation in terms of speed and area occupied is compared with the previously reported Vedic multiplier architectures. Using 90 nm technologies, the Power Delay Product (PDF) of the proposed Vedic multiplier gets reduced through KSA by 86.41% compared to the multipliers. The Vedic adder power is reduced by 45.9% when it is compared with the carry look-ahead adder. The overall power delay product is reduced around 55–60% through the FFT processor by using Vedic mathematics.

数字信号处理（DSP）是一个非常重要且活跃的研究领域。高吞吐量是大多数无线通信系统的要求。影响通信能力的关键瓶颈是快速傅立叶变换（FFT），这是大多数调制器的本质。当前，浮点FFT处理器已用于雷达信号处理，快速卷积，频谱估计和基于OFDM的调制器/解调器中。实时FFT处理需要基于VLSI的高效架构。乘法限制了FFT吞吐量的性能。因此，需要具有较小的截断误差的高速和低功率乘法器架构。本文提出了一种使用吠陀数学的改进的二进制浮点乘法器，并且已经提出了对先前公开的吠陀乘法器电路的修改。整个设计已在Verilog HDL中实现。使用Xilinx ISE Design Suite 14.5进行综合和仿真。将速度和占用面积方面的性能评估与先前报道的Vedic乘法器架构进行比较。与乘法器相比，采用90 nm技术的拟议Vedic乘法器的功率延迟乘积（PDF）通过KSA降低了86.41％。与提前进位加法器相比，吠陀加法器的功率降低了45.9％。通过使用Vedic数学，通过FFT处理器，总的功率延迟积降低了大约55-60％。整个设计已在Verilog HDL中实现。使用Xilinx ISE Design Suite 14.5进行综合和仿真。将速度和占用面积方面的性能评估与先前报道的Vedic乘法器架构进行比较。与乘法器相比，采用90 nm技术的拟议Vedic乘法器的功率延迟乘积（PDF）通过KSA降低了86.41％。与提前进位加法器相比，吠陀加法器的功率降低了45.9％。通过使用Vedic数学，通过FFT处理器，总的功率延迟积降低了大约55-60％。整个设计已在Verilog HDL中实现。使用Xilinx ISE Design Suite 14.5进行综合和仿真。将速度和占用面积方面的性能评估与先前报道的Vedic乘法器架构进行比较。与乘法器相比，采用90 nm技术的拟议Vedic乘法器的功率延迟乘积（PDF）通过KSA降低了86.41％。与提前进位加法器相比，吠陀加法器的功率降低了45.9％。通过使用Vedic数学，通过FFT处理器，总的功率延迟积降低了大约55-60％。在速度和占用面积方面的性能评估与先前报道的Vedic乘法器体系结构进行了比较。与乘法器相比，采用90 nm技术的拟议Vedic乘法器的功率延迟乘积（PDF）通过KSA降低了86.41％。与提前进位加法器相比，吠陀加法器的功率降低了45.9％。通过使用Vedic数学，通过FFT处理器，总的功率延迟积降低了大约55-60％。在速度和占用面积方面的性能评估与先前报道的Vedic乘法器体系结构进行了比较。与乘法器相比，采用90 nm技术的拟议Vedic乘法器的功率延迟乘积（PDF）通过KSA降低了86.41％。与提前进位加法器相比，吠陀加法器的功率降低了45.9％。通过使用Vedic数学，通过FFT处理器，总的功率延迟积降低了大约55-60％。