The recording of biopotential signals using techniques such as electroencephalography (EEG) and electrocardiography (ECG) poses important challenges to the design of the front-end readout circuits in terms of noise, electrode DC offset cancellation and motion artifact tolerance. In this paper, we present a 2 ^nd -order hybrid-CTDT Δ∑-∑ modulator front-end architecture that tackles these challenges by taking advantage of the over-sampling and noise-shaping characteristics of a traditional Δ∑ modulator, while employing an extra ∑-stage in the feedback loop to remove electrode DC offsets and accommodate motion artifacts. To meet the stringent noise requirements of this application, a capacitively-coupled chopper-stabilized amplifier located in the forward path of the modulator loop serves simultaneously as an input stage and an active adder. A prototype of this direct-to-digital front-end chip is fabricated in a standard 0.18-μm CMOS process and achieves a peak SNR of 105.6 dB and a dynamic range of 108.3 dB, for a maximum input range of 720 mV _pp . The measured input-referred noise is 0.98 μV _rms over a bandwidth of 0.5–100 Hz, and the measured CMRR is >100 dB. ECG and EEG measurements in human subjects demonstrate the capability of this architecture to acquire biopotential signals in the presence of large motion artifacts.

中文翻译：

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具有 720 mVpp 输入范围和 >±300 mV 偏移去除的 108 dB DR Δ∑-∑M 前端，用于多参数生物电位记录

使用脑电图 (EEG) 和心电图 (ECG) 等技术记录生物电位信号对前端读出电路的设计在噪声、电极 DC 偏移消除和运动伪影容限方面提出了重要挑战。在本文中，我们提出了一个2 ^次 阶混合 CTDT Δ∑-∑ 调制器前端架构，通过利用传统 Δ∑ 调制器的过采样和噪声整形特性来应对这些挑战，同时在反馈回路中采用额外的 ∑ 级以去除电极直流偏移并适应运动伪影。为了满足此应用的严格噪声要求，位于调制器环路前向路径中的电容耦合斩波稳定放大器同时用作输入级和有源加法器。这种直接数字化前端芯片的原型采用标准 0.18-μm CMOS 工艺制造，峰值 SNR 为 105.6 dB，动态范围为 108.3 dB，最大输入范围为 720 mV _pp 。测得的输入参考噪声为 0.98 μV _rms在 0.5–100 Hz 的带宽上，测得的 CMRR > 100 dB。人体的 ECG 和 EEG 测量证明了该架构在存在大运动伪影的情况下获取生物电势信号的能力。