In this work, ISFET frontends utilising the direct tunneling current to eliminate trapped charge are proposed. The principle has been investigated and verified via silicon-imitated ISFET first, where silicon capacitors are used to imitate the passivation ones. Because the dominant tunneling components depend on the potential difference between Gate and Drain terminals, a source-follower structure could itself perform a highpass filter with time constant at 10-100 seconds level. Additionally, a time-constant regulation mechanism is presented by feeding the output signal back to the drain terminal of ISFETs, achieving a regulation factor over 50, namely from 4.7 seconds to 243.4 seconds in our implementation. Afterwards in chemical test, proposed ISFETs have been verified in terms of unit passivation capacitance, linearity, noise and sensitivity for ISFETs with 3 different top metal areas. It is found that approximately 30 mV/pH sensitivity can be achieved, and for the first time we managed to derive the relation between chemical flicker noise and sensing metal area.

中文翻译：

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通过直接隧穿原理设计用于CMOS ISFET的极低截止频率高通前端。

在这项工作中，提出了利用直接隧穿电流消除捕获电荷的ISFET前端。首先通过仿硅的ISFET对原理进行了研究和验证，其中使用了硅电容器来模仿钝化电容器。由于主要的隧穿分量取决于栅极和漏极端子之间的电势差，因此源极跟随器结构本身可以执行高通滤波器，其时间常数为10-100秒。此外，通过将输出信号反馈到ISFET的漏极端子，提出了一种时间恒定的调节机制，实现了超过50的调节因子，即在我们的实现中为4.7秒至243.4秒。之后的化学测试中，建议的ISFET已通过单位钝化电容，线性度，具有3个不同顶部金属区域的ISFET的噪声和灵敏度。发现可以达到大约30 mV / pH的灵敏度，并且我们首次设法推导了化学闪烁噪声和感测金属面积之间的关系。