This paper presents a ternary half adder and a 1-trit multiplier using carbon nanotube transistors. The proposed circuits are designed using pass transistor logic and dynamic logic. Ternary logic uses less connections than binary logic, and less voltage changes are required for the same amount of data transmission. Carbon nanotube transistors have advantages over MOSFETs, such as the same mobility for electrons and holes, the ability to adjust the threshold voltage by changing the nanotube diameter, and less leakage power. The proposed half adder has lower power consumption, delay, and fewer transistors compared to recent ternary half adders that use similar design methods. The proposed 1-trit multiplier also has a lower delay than other designs. Moreover, these advantages are achieved over a wide supply voltage range, operating temperatures, and output loads. The design is also more robust to process variations than the nearest design in terms of PDP.

本文介绍了一种使用碳纳米管晶体管的三进制半加法器和1-trit乘法器。所提出的电路是使用传输晶体管逻辑和动态逻辑设计的。三元逻辑使用的连接少于二进制逻辑，并且对于相同数量的数据传输，所需的电压变化较小。碳纳米管晶体管具有优于MOSFET的优势，例如对于电子和空穴具有相同的迁移率，通过改变纳米管直径来调整阈值电压的能力以及较小的泄漏功率。与使用类似设计方法的最新三元半加法器相比，所建议的半加法器具有更低的功耗，延迟和更少的晶体管。提出的1-trit乘法器也具有比其他设计更低的延迟。而且，这些优点是在很宽的电源电压范围，工作温度，和输出负载。与最近的PDP设计相比，该设计在处理变化方面也更强大。