At the L/S band, the digital array radars with digital beam-forming characteristics require a compact RF module for a plane array. Such an RF module would require a small-sized local clock generation to synchronize with the central distributed clock signal. This paper proposes a 0.04mm², broadband local clock generation for the RF module in digital array radar. In such a multi-band digital array radar, the linearity of the clock generator is a bottleneck. A linearity enhanced algorithm for switched-capacitor digitally-assisted oscillators is proposed in this paper. In this linearity enhancement technique, a calibration resistor array is used to improve frequency-tuning characteristics. The digitally-assisted oscillator has a highly linearized frequency tuning curve without demanding much more power and silicon area. A prototype is fabricated using a 55-nm CMOS process. From measurement, it has a frequency tuning range from 1.3 GHz to 2.5 GHz while occupying 225 × 180 μm². The measured coarse bank tuning maximum DNL is 0.39 LSB, and the maximum INL is 4.64 LSB, which has been reduced to 43% of the other state-of-art work. The maximum power consumption is 15.8 mW from a 1.2 V supply voltage.

在L / S频段，具有数字波束形成特性的数字阵列雷达需要用于平面阵列的紧凑型RF模块。这样的RF模块将需要小尺寸的本地时钟生成以与中央分布式时钟信号同步。本文提出了0.04mm ²，用于数字阵列雷达中的RF模块的宽带本地时钟生成。在这样的多频带数字阵列雷达中，时钟发生器的线性是瓶颈。提出了一种开关电容数字辅助振荡器的线性增强算法。在这种线性度增强技术中，使用校准电阻器阵列来改善频率调谐特性。数字辅助振荡器具有高度线性化的频率调谐曲线，而无需更多的功率和硅片面积。使用55纳米CMOS工艺制造了原型。从测量，它具有从1.3到2.5GHz的频率调谐范围，同时占用225×180微米²。测得的粗调调谐最大DNL为0.39 LSB，最大INL为4.64 LSB，已减少至其他最新工艺的43％。从1.2 V电源电压开始，最大功耗为15.8 mW。