This work presents a 24 GHz integrated Phase-Locked Loop in a 60 GHz sliding-IF transceiver for IEEE 802.15.3c standard with low phase noise. For low phase noise, a varactor and MOM cap combination method is applied in this 24 GHz PLL. The capacitor bank is optimized to decrease the noise folding from circuit noise to phase noise within this method. This analog PLL is fabricated in a 65 nm CMOS technology with a phase noise of −98.8 dBc/Hz@1MHz, and the reference spur is −62.4 dBc. The power consumption of the PLL is 45.6 mW, including the output buffer.

中文翻译：

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适用于65 nm CMOS的60 GHz滑动IF收发器的低相位噪声的24 GHz PLL

这项工作在60 GHz滑移IF收发器中提供了一个24 GHz集成锁相环，用于IEEE 802.15.3c标准，具有低相位噪声。为了降低相位噪声，在此24 GHz PLL中采用了变容二极管和MOM电容组合方法。该方法优化了电容器组，以减少从电路噪声到相位噪声的噪声折叠。该模拟PLL采用65 nm CMOS技术制造，相位噪声为−98.8 dBc / Hz @ 1MHz，基准杂散为−62.4 dBc。包括输出缓冲器在内，PLL的功耗为45.6 mW。