This paper presents a half-select disturb free single-ended 9T SRAM cell with feedback-cutting mechanism to improve the write ability and isolated read path to enhance the read stability. The proposed cell is designed based on transition-metal dichalcogenide field-effect devices (TMDFETs). HSPICE simulations are performed with 10 nm TMDFET devices at 0.7 V power supply voltage for evaluation purposes. This cell increases writing noise margin to 2.13x and 1.33x compared to DI12T and 9T cells, respectively. Given that the proposed cell is single-ended type, it therefore reduces the dynamic power consumption about 50% compared to differential cells. The results show the dynamic power reduction of 51.26%, 64.54% and 45.77% compared to DI12T, 9T and UV10T cells, respectively. Also, we achieved read delay reduction of 14.49%, 14.65% and 22.04%, compared to DI12T, 9T and UV10T cells. respectively.

本文提出了一种具有反馈切断机制的半选择无干扰单端9T SRAM单元，以提高写入能力，并提供隔离的读取路径以增强读取稳定性。拟议中的电池是基于过渡金属二卤化物场效应器件（TMDFET）设计的。HSPICE仿真是在0.7 V电源电压下使用10 nm TMDFET器件进行的，以进行评估。与DI12T和9T单元相比，此单元将写入噪声容限分别提高到2.13倍和1.33倍。鉴于拟议的电池为单端类型，因此与差分电池相比，它可将动态功耗降低约50％。结果表明，与DI12T，9T和UV10T电池相比，动态功耗分别降低了51.26％，64.54％和45.77％。此外，我们的读取延迟减少了14.49％，14.65％和22.04％，与DI12T，9T和UV10T电池相比。分别。