A new Parallel Prefix Adder (PPA) based on the Ladner-Fischer is presented in this paper. The logic level of the proposed adder same as Ladner-Fischer is equal to $"\left(\log \text{N}\right)+1"$. The cell fanout in the critical delay path of Ladner-Fischer is reduced in the proposed design. Delay is improved in the proposed adder because of equal logic level in both of Ladner-Fischer with fewer cells fanout in the critical delay path of proposed structure and this delay improvement grows continuously by increasing the bit-width. Also, using full-swing Pass Transistor Logic (PTL) instead of CMOS cells for improving the performance of adders is presented. The outputs of PTL gates are always strong "0" and "1" similar to CMOS cells, also the power and delay of CMOS cells are enhanced in full-swing PTL gates. The simulations are performed in 65nm/180nm standard CMOS technologies. According to the simulation results, the average improvement in Power-Delay-Product (PDP) of proposed adder than Ladner-Fischer with PTL cells (16, 32, 64, 128, and 256-bit) in 65nm(180nm) is 24.869%(24.586%).

本文提出了一种基于Ladner-Fischer的新型并行前缀加法器（PPA）。建议的加法器与Ladner-Fischer的逻辑电平等于$”（\mathrm{日志}\text{ñ}）+\mathrm{1个}”$。所提出的设计减少了Ladner-Fischer关键延迟路径中的信元扇出。所提出的加法器中的延迟得到了改善，因为在所提出的结构的关键延迟路径中，Ladner-Fischer中的逻辑电平相等，单元扇出较少，并且这种延迟的改进通过增加位宽而不断增长。此外，还提出了使用全摆幅晶体管晶体管（PTL）而不是CMOS单元来提高加法器的性能。与CMOS单元相似，PTL栅极的输出始终为强“ 0”和“ 1”，在全摆幅PTL栅极中，CMOS单元的功率和延迟也得到了增强。仿真是在65nm / 180nm标准CMOS技术中执行的。根据仿真结果，24.869％（24.586％）。