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A 4GS/s 8‐bit time‐interleaved SAR ADC with an energy‐efficient architecture in 130 nm CMOS
International Journal of Circuit Theory and Applications ( IF 1.581 ) Pub Date : 2021-05-02 , DOI: 10.1002/cta.3029
Fredy Solis, Álvaro Fernández Bocco, Agustín C. Galetto, Leandro Passetti, Mario R. Hueda, Benjamín T. Reyes

This paper presents the design, implementation, and measurements of a 4 GS/s, 8‐bit resolution, time‐interleaved (TI) analog‐to‐digital converter (ADC) comprised of 32 asynchronous successive approximation register (SAR) ADCs. The chip is fabricated in a 130 nm CMOS process. This prototype achieves the highest sampling rate and the best efficiency for a SAR TI‐ADC in the process used. An energy‐efficient hierarchical T&H architecture, ranked in a 4 × 8 structure, has been used to interleave the aforementioned high number of SAR ADCs avoiding the power hungry buffers typically used in the input signal path and/or T&H outputs. The sampling architecture includes programmable delay cells with up to 104 fs resolution to calibrate sampling time errors. Additionally, the input matching network uses an on‐chip inductance to mitigate the impact of the packaging on the analog bandwidth. An efficient SAR ADC implementation is achieved by an optimized comparator design, which allows for both, noise and asynchronous clock control, and includes background DC offset calibration. The test chip is the core of a measurement platform dedicated to the evaluation of mismatch calibration techniques for ADCs used in high speed digital communication systems. To enable this application, a 32Gb/s low‐voltage differential signaling interface is included to transmit the samples off‐chip without any decimation. The TI‐ADC achieves a peak 7.09 effective number of bits (ENOB) (5.47ENOB at Nyquist) and 1.3 GHz input bandwidth with a power consumption of 93 mW at 1.2 V. Each SAR ADC channel achieves a Walden figure of merit (FOM) of 123fJ/conv‐step and owing to the efficient interleaved architecture the full TI‐ADC achieves a peak FOM of 171fJ/conv‐step (526fJ/conv‐step at Nyquist).

中文翻译:

具有130nm CMOS的节能架构的4GS / s 8位时间交错SAR ADC

本文介绍了由32个异步逐次逼近寄存器(SAR)ADC组成的4 GS / s,8位分辨率,时间交织(TI)模数转换器(ADC)的设计,实现和测量。该芯片采用130 nm CMOS工艺制造。该原型在所使用的过程中为SAR TI‐ADC实现了最高的采样率和最佳效率。高效的分层T&H架构,排在4×8中这种结构已被用于交错插入上述大量的SAR ADC,从而避免了通常在输入信号路径和/或T&H输出中使用的功率消耗缓冲器。采样架构包括可编程延迟单元,分辨率高达104 fs,以校准采样时间误差。此外,输入匹配网络使用片上电感来减轻封装对模拟带宽的影响。通过优化的比较器设计可实现有效的SAR ADC,该比较器设计可同时进行噪声和异步时钟控制,并包括背景DC偏移校准。该测试芯片是专用于评估高速数字通信系统中使用的ADC失配校准技术的测量平台的核心。要启用此应用程序,包含一个32Gb / s的低压差分信号接口,可在不进行任何抽取的情况下将样本传输到芯片外。TI‐ADC实现了7.09峰值有效位数(ENOB)(奈奎斯特为5.47ENOB)和1.3 GHz输入带宽,在1.2 V时的功耗为93 mW。每个SAR ADC通道均实现了Walden品质因数(FOM)。效率高达123fJ / conv-step,由于高效的交错架构,整个TI-ADC的峰值FOM达到171fJ / conv-step(奈奎斯特为526fJ / conv-step)。
更新日期:2021-05-04
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