Rapid single-flux-quantum (RSFQ) circuits are developing rapidly, but there are still many layouts that need to be completed manually, greatly reducing the design efficiency. We report the shape constraints of Josephson transmission line (JTL), and then propose automatic placement and routing methods for RSFQ circuits. First, for the pipeline structure of concurrent-flow clocking, a detailed placement algorithm based on simulated annealing is proposed, which use D Flip-Flop (DFF) insertion, column placement, and intra-column perturbation strategies to ensure the synchronization of clock phase while completing the placement of logic cells. More importantly, for the shape constraints of JTL, a new two-step JTL routing method is proposed. The first step is dummy wire routing, and the shape violations and routing congestion caused by shape constraints are solved to search legal paths for JTL routing; in the second step, timing optimization is performed when replacing dummy wire with JTL cells. Experimental results show that the proposed automatic methods achieve a 5% area-reduction and a 20× speed-up compared to manual design.

中文翻译：

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RSFQ电路中考虑JTL形状约束的布局和布线方法

快速单通量量子（RSFQ）电路发展迅速，但仍有许多布局需要手动完成，大大降低了设计效率。我们报告了约瑟夫森传输线（JTL）的形状约束，然后提出了RSFQ电路的自动布局和布线方法。首先，针对并发时钟的流水线结构，提出了一种基于模拟退火的详细布局算法，该算法采用D触发器（DFF）插入，列布局和列内扰动策略来确保时钟相位的同步。同时完成逻辑单元的放置。更重要的是，针对JTL的形状约束，提出了一种新的两步JTL路由方法。第一步是虚拟导线布线，解决了形状约束导致的形状违规和路由拥塞，为JTL路由查找合法路径。在第二步中，当用JTL单元替换虚拟导线时执行时序优化。实验结果表明，与手动设计相比，所提出的自动方法可将面积减少5％，并将速度提高20倍。