This brief presents a capacitor-less digital low-dropout (DLDO) regulator, which has low steady-state voltage ripples ( $V_{RIPP}$ ) and low output noise, suitable for driving analog circuits in system-on-chip devices. To reduce $V_{RIPP}$ , a steady-state control based on $\Delta \Sigma $ modulation and a clock multiplication technique are proposed. Thanks to the $\Delta \Sigma $ operation, the proposed DLDO generates noise-shaped output voltage ( $V_{OUT}$ ), reducing $V_{RIPP}$ and improving its noise performance without using an output capacitor. The $\Delta \Sigma $ -modulator-based controller is activated just during the steady state, triggered by a lock detector, which continuously tracks $V_{OUT}$ and compares it to a reference $V_{REF}$ . During the steady state, a cyclic time-to-pulse converter and a clock combiner generate an oversampling clock for the controller. The proposed DLDO was fabricated in a 110-nm CMOS process with an active area of 0.07 $mm^{2}$ . The measurement results demonstrate that at $V_{OUT} = 0.5$ V, $V_{DD} = 0.6$ V, and $I_{LOAD} = 500\,\,\mu \text{A}$ , the proposed DLDO achieves <1 mV of $V_{RIPP}$ , 17.5 dB of power supply rejection (PSR) at 1 MHz, and $-151\,\,\text{V}^{2}rms/$ Hz (dB) of power-spectral density at 51.2 kHz. Furthermore, the proposed DLDO achieves 99.77% of current efficiency and 0.25 mV/mA of load regulation while driving the maximum $I_{LOAD}$ of 40 mA.

中文翻译：

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具有基于ΔΣ调制的纹波抑制功能的无电容双模全数字LDO

本简介介绍了一种无电容数字低压降（DLDO）稳压器，该稳压器具有较低的稳态电压纹波（ $ V_ {RIPP} $ ）和低输出噪声，适合于驱动片上系统设备中的模拟电路。减少 $ V_ {RIPP} $ ，基于 $ \ Delta \西格玛$ 提出了调制和时钟乘法技术。非常感谢 $ \ Delta \西格玛$ 操作中，建议的DLDO会产生噪声形的输出电压（ $ V_ {OUT} $ ），减少 $ V_ {RIPP} $ 并在不使用输出电容器的情况下改善其噪声性能。这 $ \ Delta \西格玛$ 基于调制器的控制器仅在稳定状态期间由锁定检测器触发，该检测器不断跟踪 $ V_ {OUT} $ 并将其与参考进行比较 $ V_ {REF} $ 。在稳态期间，一个循环时间脉冲转换器和一个时钟组合器为控制器生成一个过采样时钟。拟议的DLDO采用110纳米CMOS工艺制造，有效面积为0.07 $ mm ^ {2} $ 。测量结果表明 $ V_ {OUT} = 0.5 $ V， $ V_ {DD} = 0.6 $ V，和 $ I_ {LOAD} = 500 \，\，\ mu \ text {A} $ ，建议的DLDO达到<1 mV的 $ V_ {RIPP} $ ，1 MHz时17.5 dB的电源抑制（PSR），以及 $ -151 \，\，\ text {V} ^ {2} rms / $ 51.2 kHz处的功率谱密度的Hz（dB）。此外，拟议的DLDO可在驱动最大功率的同时实现99.77％的电流效率和0.25 mV / mA的负载调节。 $ I_ {LOAD} $ 40 mA。